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A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction Conference paper
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, 12-15 Sept. 2016
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:16/0  |  Submit date:2019/02/11
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 2,Page: 365-377
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan (Ben) U;  Rui Paulo Martins
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Analog-to-digital Conversion  Interleaving  Interpolation  Multibit/cycle Sar  Offset Calibration  
Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2015,Volume: 62,Issue: 9,Page: 2196-2206
Authors:  Jianyu Zhong;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:11/0  |  Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Reference Noise  Successive-approximation-register (Sar) Adc  Thermal Noise  
A 123-phase DC-DC converter-ring with fast-DVS for microprocessors Conference paper
2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco, CA, United states, 22-26 Feb. 2015
Authors:  Yan Lu;  Junmin Jiang;  Wing-Hung Ki;  C. Patrick Yue;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:12/0  |  Submit date:2018/11/06
A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS Conference paper
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, PEOPLES R CHINA, MAY 19-23, 2013
Authors:  Wen-Lan Wu;  Yan Zhu;  Li Ding;  Chi-Hang Chan;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:12/0  |  Submit date:2019/02/11
A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS Conference paper
2012 Proceedings of the ESSCIRC (ESSCIRC), Bordeaux, France, 17-21 Sept. 2012
Authors:  Guohe Yin;  He-Gong Wei;  U–Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Zhihua Wang;  Rui Paulo Martins
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Analgo-to-digital Converter  Successive Approximation Register  Ultra-low Power  Sensor Applications  
A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure Conference paper
2012 Symposium on VLSI Circuits (VLSIC), Honolulu, HI, USA, 13-15 June 2012
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
A 10-bit SAR ADC with two redundant decisions and splitted-MSB-cap DAC array Conference paper
2012 IEEE Asia Pacific Conference on Circuits and Systems, Kaohsiung, TAIWAN, DEC 02-05, 2012
Authors:  Wen-Lan Wu;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
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Multi-merged-switched redundant capacitive DACs for 2b/cycle SAR ADC Conference paper
Midwest Symposium on Circuits and Systems, Yonsei Univ, Seoul, SOUTH KOREA, AUG 07-10, 2011
Authors:  Zhong J.;  Zhu Y.;  Sin S.-W.;  U S.-P.;  Martins R.P.
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A power effective 5-bit 600 MS/s binary-search ADC with simplified switching Conference paper
Midwest Symposium on Circuits and Systems, Seattle, WA, AUG 01-04, 2010
Authors:  Wong S.S.;  Chio U.-F.;  Choi H.-L.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:9/0  |  Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Asynchronous Binary-search Adc