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A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators Conference paper
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, Kuala Lumpur, MALAYSIA, DEC 06-09, 2010
Authors:  Jiang Y.;  Wong K.-F.;  Cai C.-Y.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite  |  View/Download:9/0  |  Submit date:2019/02/11
Clock-jitter Sensitivity  Continuous-time  Sigma-delta Modulator  Switched Current Dac  
A pseudo-differential comparator-based pipelined ADC with common mode feedforward technique Conference paper
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, Macao, PEOPLES R CHINA, NOV 30-DEC 03, 2008
Authors:  Ding L.;  Chan S.;  Wong K.-F.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
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