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A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017,Volume: 64,Issue: 7,Page: 1684-1695
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:14/0  |  Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Low Power  Successive Approximation Architecture  Switched-capacitor Circuits  
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017,Volume: 25,Issue: 1,Page: 354-363
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Pan, Seng U.;  Martins, Rui Paulo
Favorite  |  View/Download:15/0  |  Submit date:2018/10/30
Offset Calibration  Partial Interleaving (Pi)  Pipelined-sar  Stage-gain Error Calibration  
A Sub-GHz wireless transmitter utilizing a multi-class-linearized PA and time-domain wideband-auto I/Q-LOFT calibration for IEEE 802.11af WLAN Journal article
IEEE Transactions on Microwave Theory and Techniques, 2015,Volume: 63,Issue: 10,Page: 3228-3241
Authors:  Ka-Fai Un;  Wei-Han Yu;  Chak-Fong Cheang;  Gengzhen Qi;  Pui-In Mak;  Rui P. Martins
Favorite  |  View/Download:4/0  |  Submit date:2019/02/11
Adjacent Channel Leakage Ratio (Aclr)  Cmos  Digital Calibration  Gm-c Low-pass Filter  Harmonic Rejection Mixer (Hrm)  Harmonic Rejection Ratio (Hrr)  Ieee 802.11af  Image Rejection Ratio (Irr)  In-phase/quadrature (I/q) Imbalance  Lo Feedthrough (Loft)  Lo-leakage Rejection Ratio (Lrr)  Local Oscillator (Lo)  Power Amplifier (Pa)  Transmitter (Tx)  Wideband  
A 50-fJ 10-b 160-MS/s pipelined-SAR ADC decoupled flip-around MDAC and self-embedded offset cancellation Journal article
IEEE Journal of Solid-State Circuits, 2012,Volume: 47,Issue: 11,Page: 2614-2626
Authors:  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins;  Franco Maloberti
Favorite  |  View/Download:12/0  |  Submit date:2018/10/30
Decoupled Flip-around Mdac  Offset-cancellation  Pipelined-sar Adc  Vdd -attenuator  
Inter-Stage Gain Error self-calibration of a 31.5fJ 10b 470MS/S pipelined-SAR ADC Conference paper
2012 IEEE Asian Solid State Circuits Conference (A-SSCC), Kobe, JAPAN, NOV 12-14, 2012
Authors:  Jianyu Zhong;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui P. Martins
Favorite  |  View/Download:11/0  |  Submit date:2019/02/11