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A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Honolulu, HI, USA, 18-22 June 2018
Authors:  Song Y.;  Zhu Y.;  Chan C.-H.;  Geng L.;  Martins R.P.
Favorite  |  View/Download:18/0  |  Submit date:2019/02/11
A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 9,Page: 3014-3026
Authors:  Chen Y.;  Mak P.-I.;  Boon C.C.;  Martins R.P.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
Bandwidth (Bw)  Cmos  Cross-quadrature Clocking  D-type Flip-flop (Dff)  Data-dependent Jitter (Ddj)  Duobinary  Figure-of-merit (Fom)  Latch  Multi-level Signaling  Multiplexer (Mux)  Selector  Timing Margin  
Thyristor controlled LC compensator for compensating dynamic reactive power Patent
专利类型: 发明专利, 专利号: US009960599B1,
Authors:  Lei Wang;  Man - Chung Wong;  Chi - Seng Lam
Favorite  |  View/Download:3/0  |  Submit date:2019/04/08
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download:23/0  |  Submit date:2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 3,Page: 572-583
Authors:  Qiu, Lei;  Tang, Kai;  Zheng, Yuanjin;  Siek, Liter;  Zhu, Yan;  U, Seng-Pan
Favorite  |  View/Download:13/0  |  Submit date:2018/10/30
Digital Background Calibration  Subradix-2  Successive Pproximation Register (Sar) Analog-to-digital Converters (Adcs)  Time Interleaved (Ti)  Time Skew  
Analysis of the Effects of Operation Voltage Range in Flexible DC Control on Railway HPQC Compensation Capability in High-Speed Co-phase Railway Power Journal article
IEEE Transactions on Power Electronics, 2018,Volume: 33,Issue: 2,Page: 1760-1774
Authors:  Keng-Weng Lao;  Man-Chung Wong;  Ningyi Dai;  Chi-Seng Lam;  Lei Wang;  Chi-Kong Wong
Favorite  |  View/Download:18/0  |  Submit date:2018/10/30
Co-phase Traction Power Supply  Flexible Dc Voltage Control  High-speed Railway  Power Quality  Railway Hybrid Power Quality Conditioner (Hpqc)  
Fully Integrated Inductor-Less Flipping-Capacitor Rectifier for Piezoelectric Energy Harvesting Journal article
IEEE Journal of Solid-State Circuits, 2017,Volume: 52,Issue: 12,Page: 3168-3180
Authors:  Zhiyuan Chen;  Man-Kay Law;  Pui-In Mak;  Wing-Hung Ki;  Rui P. Martins
Favorite  |  View/Download:11/0  |  Submit date:2019/02/11
Cmos  Deep-tissue Implant  Flipping-capacitor Rectifier (Fcr)  Fully Integrated  High Efficiency  Inductor-less  Parallel-synchronized-switch Harvesting-on-inductor (P-sshi)  Piezoelectric Energy Harvesting  Reconfigurable Capacitor Array  Ultrasound  
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017,Volume: 52,Issue: 10,Page: 2576-2588
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Li, Cheng;  Zhang, Wai-Hong;  Ho, Iok-Meng;  Wei, Lai;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download:16/0  |  Submit date:2018/10/30
Reference Buffer  Reference Error Calibration  Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Threshold Reconfigurable Comparator  
A 27-Gb/s Time-Interleaved Duobinary Transmitter Achieving 1.44-mW/Gb/s FOM in 65-nm CMOS Journal article
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2017,Volume: 27,Issue: 9,Page: 839-841
Authors:  Chen, Yong;  Mak, Pui-In;  Boon, Chirn Chye;  Martins, Rui P.
Favorite  |  View/Download:8/0  |  Submit date:2018/10/30
Cmos  Duobinary  Figure-of-merit (Fom)  Flip-flop (Ff)  Latch  Multiplexer (Mux)  Selector  Time-interleaved  
Analysis in the Effect of Co-phase Traction Railway HPQC Coupled Impedance on Its Compensation Capability and Impedance-Mapping Design Technique Based on Required Compensation Capability for Reduction in Operation Voltage Journal article
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2017,Volume: 32,Issue: 4,Page: 2631-2646
Authors:  Keng-Weng Lao;  Man-Chung Wong;  NingYi Dai;  Chi-Seng Lam;  Chi-Kong Wong;  Lei Wang
Favorite  |  View/Download:19/0  |  Submit date:2018/10/30
Co-phase Traction Power Supply  High-speed Railway  Impedance Mapping  Power Quality  Railway Hybrid Power Quality Conditioner (Hpqc)