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A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download:23/0  |  Submit date:2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control Conference paper
2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 5-9 Feb. 2017
Authors:  Mo Huang;  Yan Lu;  Seng-Pan U;  Rui P. Martins
Favorite  |  View/Download:8/0  |  Submit date:2018/11/06
A Single-Chip Solar Energy Harvesting IC Using Integrated Photodiodes for Biomedical Implant Applications Journal article
IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, 2017,Volume: 11,Issue: 1,Page: 44-53
Authors:  Zhiyuan Chen;  Man-Kay Law;  Pui-In Mak;  Rui P. Martins
Favorite  |  View/Download:21/0  |  Submit date:2018/10/30
Auxiliary Charge Pump  Charge Pump/solar Cell Area Optimization  Photodiode-assisted Dual Startup Circuit  Single-chip Solar Energy Harvesting  
Metastablility in SAR ADCs Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2017,Volume: 64,Issue: 2,Page: 111-115
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Boris Murmann;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:14/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Comparator  Metastability  Successive Approximation Register (Sar)  
A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction Conference paper
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, 12-15 Sept. 2016
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:13/0  |  Submit date:2019/02/11
A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2016,Volume: 63,Issue: 7,Page: 683-687
Authors:  Huang M.;  Lu Y.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
Burst Mode  Coarse-fine-tuning (Cft)  Digital Control  Dynamic Voltage Scaling (Dvs)  Energy-efficient Digital  Fast Transient  Low Dropout Regulator (Ldo)  
A 1.1 μW CMOS smart temperature sensor with an inaccuracy of ±0.2 °C (3σ) for clinical temperature monitoring Journal article
IEEE Sensors Journal, 2016,Volume: 16,Issue: 8,Page: 2272-2281
Authors:  Man-Kay Law;  Sanfeng Lu;  Tao Wu;  Amine Bermak;  Pui-In Mak;  Rui P. Martins
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
Smart Temperature Sensor  Ultra-low Power  High Accuracy  Incremental Analog-to-digital Converter (I-adc),  Multi-ratio Pre-gain  Block-based Data Weighted Averaging (Bdwa)  
Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques Conference paper
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), Macau, China, JAN 25-28, 2016
Authors:  Ming-Zhong Li;  Chio-In Ieong;  Man-Kay Law;  Pui-In Mak;  Mang-I Vai;  Sio-Hang Pun;  Rui P. Martins
Favorite  |  View/Download:15/0  |  Submit date:2019/02/11
A digital LDO with transient enhancement and limit cycle oscillation reduction Conference paper
2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, South Korea, 25-28 Oct. 2016
Authors:  Mo Huang;  Yan Lu;  Seng-Pan U;  Rui P. Martins
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
Low Dropout Regulator (Ldo)  Digital Control  Coarse-fine-tuning (Cft)  Burst-mode  Limit Cycle Oscillation (Lco)  Feed-forward Path  Compensation Zero  
Energy Optimized Subthreshold VLSI Logic Family with Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015,Volume: 23,Issue: 12,Page: 3119-3123
Authors:  Li M.-Z.;  Ieong C.-I.;  Law M.-K.;  Mak P.-I.;  Vai M.-I.;  Pun S.-H.;  Martins R.P.
Favorite  |  View/Download:9/0  |  Submit date:2019/02/11
Cmos  Device Sizing  Electrocardiography (Ecg)  Finite Impulse Response (Fir) Filter  Inverse Narrow Width (Inw)  Logical Effort  Process-voltage-temperature (Pvt) Variations  Subthreshold Standard Logic Library  Ultralow Energy  Ultralow Voltage.