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A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 2,Page: 157-161
Authors:  Jiang T.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:20/0  |  Submit date:2019/02/14
Bootstrap (Bt)  Low Voltage  Non-overlapping Clock  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 1,Page: 88-98
Authors:  Yang S.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:25/0  |  Submit date:2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A 0.032-mm2 0.15-V Three-Stage Charge-Pump Scheme Using a Differential Bootstrapped Ring-VCO for Energy-Harvesting Applications Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2018,Volume: 65,Issue: 2,Page: 146-150
Authors:  Yi H.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:13/0  |  Submit date:2019/02/11
Bootstrapped  Charge Pump (Cp)  Cmos  Energy Harvesting  Reverse Current  Ring-vco  Ultra-low Voltage  
A 0.003mm2 1.7-to-3.5GHz dual-mode time-interleaved ring-VCO achieving 90-to-150kHz 1/f3 phase-noise corner Conference paper
2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, United states, 1 31, 2016 - 2 4, 2016
Authors:  Jun Yin;  Pui-In Mak;  Franco Maloberti;  Rui P. Martins
Favorite  |  View/Download:13/0  |  Submit date:2018/11/06
A Time-Interleaved Ring-VCO with Reduced 1/f3 Phase Noise Corner, Extended Tuning Range and Inherent Divided Output Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 12,Page: 2979-2991
Authors:  Yin J.;  Mak P.-I.;  Maloberti F.;  Martins R.P.
Favorite  |  View/Download:12/0  |  Submit date:2019/02/11
1/f3 Phase Noise Corner  Divided Output  Flicker Noise  Impulse Sensitivity Function (Isf)  Phase Combiner  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Supply Voltage  Time-interleaved (Ti).