UM

Browse/Search Results:  1-3 of 3 Help

Filters    
Selected(0)Clear Items/Page:    Sort:
A 0.0056mm2all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrmsJitter and -249dB FOM Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, United states, 2 11, 2018 - 2 15, 2018
Authors:  Yang, Shiheng;  Yin, Jun;  Mak, Pui-In;  Martins, Rui P.
Favorite  |  View/Download:10/0  |  Submit date:2018/11/06
A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, FEB 11-15, 2018
Authors:  Shiheng Yang;  Jun Yin;  Pui-In Mak;  Rui P. Martins
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
A 0.003mm2 1.7-to-3.5GHz dual-mode time-interleaved ring-VCO achieving 90-to-150kHz 1/f3 phase-noise corner Conference paper
2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, United states, 1 31, 2016 - 2 4, 2016
Authors:  Jun Yin;  Pui-In Mak;  Franco Maloberti;  Rui P. Martins
Favorite  |  View/Download:13/0  |  Submit date:2018/11/06