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A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 2,Page: 157-161
Authors:  Jiang T.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:20/0  |  Submit date:2019/02/14
Bootstrap (Bt)  Low Voltage  Non-overlapping Clock  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 1,Page: 88-98
Authors:  Yang S.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:25/0  |  Submit date:2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter