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Inter-Stage Gain Error self-calibration of a 31.5fJ 10b 470MS/S pipelined-SAR ADC Conference paper
2012 IEEE Asian Solid State Circuits Conference (A-SSCC), Kobe, JAPAN, NOV 12-14, 2012
作者:  Jianyu Zhong;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui P. Martins
收藏  |  浏览/下载:10/0  |  提交时间:2019/02/11
A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration Conference paper
2011 Proceedings of the ESSCIRC (ESSCIRC), Helsinki, Finland, 12-16 Sept. 2011
作者:  Chio U.-F.;  Chan C.-H.;  Choi H.-L.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
收藏  |  浏览/下载:6/0  |  提交时间:2019/02/11
On-Chip Unsteady Reference Voltage Compensation Techniques for Very-High-Speed Pipelined ADC Conference paper
Proc. IEEE/IEE Regional Inter-University Post-graduate EEE Conference – RIUPEEEC 2005, Hong Kong, China, Jun. 2005
作者:  Weng-Ieng Mok;  Pui-In Mak;  Seng-Pan U;  R. P. Martins
收藏  |  浏览/下载:6/0  |  提交时间:2019/02/28
High-speed  Pipelined Analog-to-digital Converter  Reference Voltage  Voltage Buffer