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Analysis of common-mode interference and jitter of clock receiver circuits with improved topology Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 6,Page: 1819-1829
Authors:  Yang X.;  Zhu Y.;  Chan C.-H.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
Isf  Low Clock Jitter Circuit  Self-bias  
A 312 ps response-time LDO with enhanced super source follower in 28 nm CMOS Journal article
Electronics Letters, 2016,Volume: 52,Issue: 16,Page: 1368-1370
Authors:  Yan Lu;  Cheng Li;  Yan Zhu;  Mo Huang;  Seng-Pan U;  Rui P. Martins
Favorite  |  View/Download:9/0  |  Submit date:2019/02/11