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A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3606-3616
Authors:  Zhu Y.;  Chan C.-H.;  Zheng Z.-H.;  Li C.;  Zhong J.-Y.;  Martins R.P.
Favorite | View/Download：12/0 | TC[WOS]:4 TC[Scopus]:4 | Submit date：2019/02/11
passive sharing  pipelined-SAR ADC  sampling front-end design  switch bootstrap technique  Time-interleaved ADC  
A 14-Bit Split-Pipeline ADC with Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2018,Volume: 65,Issue: 10,Page: 1380-1384
Authors:  Mao J.;  Guo M.;  Sin S.-W.;  Martins R.P.
Favorite | View/Download：8/0 | TC[WOS]:3 TC[Scopus]:3 | Submit date：2019/02/11
Analog-to-digital conversion  digital background calibration  opamp-sharing technique  pipelined ADC  split ADC  
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017,Volume: 25,Issue: 1,Page: 354-363
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Pan, Seng U.;  Martins, Rui Paulo
Favorite | View/Download：31/0 | TC[WOS]:8 TC[Scopus]:8 | Submit date：2018/10/30
Offset Calibration  Partial Interleaving (Pi)  Pipelined-sar  Stage-gain Error Calibration  
Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2015,Volume: 62,Issue: 9,Page: 2196-2206
Authors:  Jianyu Zhong;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite | View/Download：16/0 | TC[WOS]:16 TC[Scopus]:16 | Submit date：2019/02/11
Analog-to-digital Converter (Adc)  Reference Noise  Successive-approximation-register (Sar) Adc  Thermal Noise  
1.2-V, 10-bit, 60– 360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 mm CMOS with minimised supply headroom Journal article
IET Circuits, Devices & Systems, 2010,Volume: 4,Issue: 1,Page: 1-13
Authors:  S.-W. Sin;  Seng-Pan U;  R.P. Martins
Favorite | View/Download：8/0 | TC[WOS]:8 TC[Scopus]:0 | Submit date：2019/02/27
A 1-V 10b 40MS/s Pipelined ADC with Low-Voltage Circuit Techniques in 0.18 um CMOS Journal article
澳門機電工程專業協會(APEMEM)會刊, 2009
Authors:  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite | View/Download：10/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date：2019/02/28
Index Terms-pipelined Adc  Low-voltage  Current-mode Comparator