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A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS Conference paper
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Zheng, Zi-Hao;  Li, Cheng;  Zhong, Jian-Yu;  Martins, Rui P.
Favorite | View/Download:51/0 | TC[WOS]:4 TC[Scopus]:4 | Submit date:2018/10/30
Time-interleaved ADC  sampling front-end design  passive sharing  pipelined-SAR ADC  switch bootstrap technique  
A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current Conference paper
Authors:  Mao, Jiaji;  Guo, Mingqiang;  Sin, Sai-Weng;  Martins, Rui Paulo
Favorite | View/Download:36/0 | TC[WOS]:3 TC[Scopus]:3 | Submit date:2018/10/30
Analog-to-digital conversion  digital background calibration  pipelined ADC  split ADC  opamp-sharing technique