UM

浏览/检索结果: 共20条,第1-10条 帮助

限定条件                
已选(0)清除 条数/页:   排序方式:
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
作者:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
收藏  |  浏览/下载:28/0  |  提交时间:2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017,Volume: 64,Issue: 7,Page: 1684-1695
作者:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
收藏  |  浏览/下载:13/0  |  提交时间:2019/02/11
Analog-to-digital Converter (Adc)  Low Power  Successive Approximation Architecture  Switched-capacitor Circuits  
A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration Conference paper
2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 5-9 Feb. 2017
作者:  Chi-Hang Chan;  Yan Zhu;  Iok-Meng Ho;  Wai-Hong Zhang;  Seng-Pan U;  Rui Paulo Martins
收藏  |  浏览/下载:14/0  |  提交时间:2018/11/06
A 4x time-domain interpolation 6-bit 3.4 Gs/s 12.6 mw flash ADC in 65 nm CMOS Journal article
Journal of Semiconductor Technology and Science, 2016,Volume: 16,Issue: 4,Page: 395-404
作者:  Jianwei Liu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
收藏  |  浏览/下载:8/0  |  提交时间:2019/02/11
4x Time-domain Interpolation  Flash Adc  Sr-latch  Time Comparator  
An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 5,Page: 1223-1234
作者:  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U;  Rui Paulo Martins
收藏  |  浏览/下载:9/0  |  提交时间:2019/02/11
Offset Calibration  Pipelined-successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Sar Logic  
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 2,Page: 365-377
作者:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan (Ben) U;  Rui Paulo Martins
收藏  |  浏览/下载:10/0  |  提交时间:2019/02/11
Analog-to-digital Conversion  Interleaving  Interpolation  Multibit/cycle Sar  Offset Calibration  
A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation Conference paper
2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), Xiamen Int C Ctr (XICC), Xiamen, PEOPLES R CHINA, 9-11 Nov. 2015
作者:  Jianwei Liu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
收藏  |  浏览/下载:5/0  |  提交时间:2019/02/11
Analog to digital converter circuit Patent
专利类型: 发明专利, 专利号: US8659461B1, 申请日期: 2012-11-13, 公开日期: 2014-02-25
作者:  Yan Zhu;  Chi Hang Chan;  Sai Weng Sin;  Seng Pan U;  Rui Paulo da Silva Martins;  Franco Maloberti
收藏  |  浏览/下载:9/0  |  提交时间:2019/03/30
An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC Conference paper
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC), Venezia Lido, ITALY, 22-26 Sept. 2014
作者:  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U;  R.P.Martins
收藏  |  浏览/下载:11/0  |  提交时间:2019/02/11
A 10.4-ENOB 120MS/s SAR ADC with DAC linearity calibration in 90nm CMOS Conference paper
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore, SINGAPORE, NOV 11-13, 2013
作者:  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U;  R.P.Martins
收藏  |  浏览/下载:6/0  |  提交时间:2019/02/11