UM

Browse/Search Results:  1-1 of 1 Help

Filters                
Selected(0)Clear Items/Page:    Sort:
Clock-jitter sensitivity reduction in CT ΣΔ modulators using voltage-crossing detection DAC Conference paper
Midwest Symposium on Circuits and Systems, Yonsei Univ, Seoul, SOUTH KOREA, AUG 07-10, 2011
Authors:  Jiang Y.;  Cai C.-Y.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11