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A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS Conference paper
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Zheng, Zi-Hao;  Li, Cheng;  Zhong, Jian-Yu;  Martins, Rui P.
Favorite  |  View/Download:26/0  |  Submit date:2018/10/30
Time-interleaved ADC  sampling front-end design  passive sharing  pipelined-SAR ADC  switch bootstrap technique  
A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018,Volume: 65,Issue: 11,Page: 1534-1538
Authors:  Wang, X. Shawn;  Jin, Xin;  Du, Jieqiong;  Li, Yilei;  Du, Yuan;  Wong, Chien-Heng;  Kuan, Yen-Cheng;  Chan, Chi-Hang;  Chang, Mau-Chung Frank
Favorite  |  View/Download:3/0  |  Submit date:2019/01/17
Analog-to-digital converter (ADC)  virtual-ground sampling  SAR  time-interleaved  
Design Considerations of Distributed and Centralized Switched-Capacitor Converters for Power Supply On-Chip Journal article
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, 2018,Volume: 6,Issue: 2,Page: 515-525
Authors:  Lu, Yan;  Jiang, Junmin;  Ki, Wing-Hung
Favorite  |  View/Download:16/0  |  Submit date:2018/10/30
Active-matrix Light-emitting Diode (Amled)  Amplifier  Charge Pump  Converter Ring  Dc-dc Converter  Digital Control  Dynamic Voltage Scaling (Dvs)  Fully Integrated Voltage Regulator (Fivr)  Hybrid Converter  Low-dropout Regulator (Ldo)  Multilevel  Multiphase  Resonant Converter  Switched-capacitor (Sc) Power Converter  Voltage-controlled Oscillator (Vco)  
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download:30/0  |  Submit date:2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 8,Page: 1966-1976
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, Rui P.;  Maloberti, Franco
Favorite  |  View/Download:27/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Flash  Time-based Dual-edge-triggered  
Split-based time-interleaved ADC with digital background timing-skew calibration Conference paper
2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Giardini Naxos, Italy, JUN 12-15, 2017
Authors:  Guo M.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:14/0  |  Submit date:2019/02/11
Adc  Converters  Digital Background Calibration  Split-adc  Time-interleaving  Timing  
A 12b 180MS/s 0.068mm(2) With Full-Calibration-Integrated Pipelined-SAR ADC Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 7,Page: 1684-1695
Authors:  Zhong, Jianyu;  Zhu, Yan;  Chan, Chi-Hang;  Sin, Sai-Weng;  U, Seng-Pan;  Martins, Rui Paulo
Favorite  |  View/Download:13/0  |  Submit date:2018/10/30
Analog-to-digital converter (ADC)  successive approximation architecture  low power  switched-capacitor circuits  
A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017,Volume: 64,Issue: 7,Page: 1684-1695
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:13/0  |  Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Low Power  Successive Approximation Architecture  Switched-capacitor Circuits  
Reconfigurable mismatch-free time-interleaved bandpass sigma-delta modulator for wireless communications Journal article
ELECTRONICS LETTERS, 2017,Volume: 53,Issue: 7,Page: 506–508
Authors:  Dongyang Jiang;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins;  Franco Maloberti
Favorite  |  View/Download:16/0  |  Submit date:2018/10/30
Sigma-delta Modulation  Modulators  Software Radio  Radio Receivers  Circuit Simulation  Band-pass Filters  Table Lookup  Reconfigurable Mismatch-free Time-interleaved Bandpass Sigma-delta Modulator  Wireless Communications  Control Parameters  Look-up Table  Path Numbers  Path Sampling Frequencies  Tuning Coefficients  Design Reconfigurability  Multiband Receiver  Software Defined Radio Systems  Behavioural Simulations  
A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration Conference paper
2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 5-9 Feb. 2017
Authors:  Chi-Hang Chan;  Yan Zhu;  Iok-Meng Ho;  Wai-Hong Zhang;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:15/0  |  Submit date:2018/11/06