UM
(Note: the search results are based on claimed items)

Browse/Search Results:  1-10 of 17 Help

Filters        
Selected(0)Clear Items/Page:    Sort:
A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017,Volume: 64,Issue: 7,Page: 1684-1695
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite | View/Download:22/0 | TC[WOS]:9 TC[Scopus]:0 | Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Low Power  Successive Approximation Architecture  Switched-capacitor Circuits  
A High DR Multi-Channel Stage-Shared Hybrid Front-End for Integrated Power Electronics Controller Conference paper
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), Toyama, JAPAN, 7-9 Nov. 2016
Authors:  Yuan Ren;  Sai-Weng Sin;  Chi-Seng Lam;  Man-Chung Wong;  Seng-Pan U;  Rui Paulo Martins
Favorite | View/Download:21/0 | TC[WOS]:3 TC[Scopus]:0 | Submit date:2018/12/23
Multi-channel Sigma Delta Front-end Interface  Programmable-gain  Integrated Pe Controller  
Resolution-enhanced sturdy MASH delta-sigma modulator for wideband low-voltage applications Journal article
Electronics Letters, 2015,Volume: 51,Issue: 14,Page: 1061-1063
Authors:  Liang Qi;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite | View/Download:13/0 | TC[WOS]:4 TC[Scopus]:0 | Submit date:2019/02/11
Analog to Digital Converter Circuit Patent
专利类型: 发明专利, 专利号: TWI446723B, 申请日期: 2011-03-08,
Authors:  Sin,S-W(冼世荣);  Ding L(丁立);  Zhu Y(诸嫣);  Wei HG(魏和功);  Chan CH(陈知行);  Chio UF(赵汝法);  U SP(余成斌);  Martins,R(马许愿);  Franco,M
Favorite | View/Download:21/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/03/30
Analog to digital converter circuit Patent
专利类型: 发明专利, 专利号: US8659461B1, 申请日期: 2012-11-13, 公开日期: 2014-02-25
Authors:  Yan Zhu;  Chi Hang Chan;  Sai Weng Sin;  Seng Pan U;  Rui Paulo da Silva Martins;  Franco Maloberti
Favorite | View/Download:18/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/03/30
Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active-passive loop-filters Journal article
Analog Integrated Circuits and Signal Processing, 2013,Volume: 76,Issue: 1,Page: 35-46
Authors:  Chen-Yan Cai;  Yang Jiang;  Sai-Weng Sin;  Seng-Pan U;  Rui P. Martins
Favorite | View/Download:8/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11
Ct Δς Modulator  Excess-loop-delay Compensation Techniques For Hybrid Active-passive Loop-filter  Excess-loop-delay For Hybrid Active-passive Loop-filter  Hybrid Active-passive Loop-filter  
Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption Patent
专利类型: 发明专利, 专利号: US8427355B2, 申请日期: 2011-09-14,
Authors:  Sai-Weng Sin;  Li Ding;  Yan Zhu;  He-Gong Wei;  Chi-Hang Chan;  U-Fat Chio;  Seng-Pan U;  Rui Paulo da Silva Martins;  Franco Maloberti
Favorite | View/Download:15/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/03/30
A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique Conference paper
2012 Proceedings of the ESSCIRC (ESSCIRC), Bordeaux, France, 17-21 Sept. 2012
Authors:  Rui Wang;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Zhihua Wang;  Rui Paulo Martins
Favorite | View/Download:8/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11
Sar Adc  Pipelined  Digital Calibration  Op-amp Sharing  
Analog to digital converter circuit Patent
专利类型: 发明专利, 专利号: TW201242261A, 申请日期: 2011-03-08, 公开日期: 2012-10-16
Authors:  Xian SR(冼世荣);  Ding L(丁立);  Zhu Y(诸嫣);  Wei HG(魏和功);  Chen ZX(陈知行);  Zhao RF(赵汝法);  余成斌 U;  Ma XY(马许愿);  马洛贝尔蒂 佛朗哥
Favorite | View/Download:21/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/04/18
Analog to digital converter circuit Patent
专利类型: 发明专利, 专利号: US20120229313A1, 申请日期: 2011-09-14, 公开日期: 2012-09-13
Authors:  Sai-Weng SIN;  He-Gong WEI;  Franco MALOBERTI;  Li DING;  Yan ZHU;  Chi-Hang CHAN;  U-Fat CHIO;  Seng-Pan U;  Rui Paulo da Silva MARTINS
Favorite | View/Download:14/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/26