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Quick and cost-efficient A/D converter static characterization using low-precision testing signal Journal article
MICROELECTRONICS JOURNAL, 2018,Volume: 74,Page: 86-93
Authors:  Qin, Wei Wei;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download:16/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Static Characterization Estimation  Adc Testing  Ramp Testing  Nonlinear Input Signal  Attenuated Input Signal  
A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 8,Page: 1966-1976
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, Rui P.;  Maloberti, Franco
Favorite  |  View/Download:27/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Flash  Time-based Dual-edge-triggered  
A sub-1V 78-nA bandgap reference with curvature compensation Journal article
MICROELECTRONICS JOURNAL, 2017,Volume: 63,Page: 35-40
Authors:  Ziyang Luo;  Yan Lu;  Mo Huang;  Junmin Jiang;  Sai-Weng Sin;  Seng-Pan U;  Rui P. Martins
Favorite  |  View/Download:29/0  |  Submit date:2018/10/30
Bandgap Reference  Cmos Analog Integrated Circuits  Internet-of-things (Iot)  Ultra-low Power  Curvature Compensation  Temperature Coefficient  
Reconfigurable mismatch-free time-interleaved bandpass sigma-delta modulator for wireless communications Journal article
ELECTRONICS LETTERS, 2017,Volume: 53,Issue: 7,Page: 506–508
Authors:  Dongyang Jiang;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins;  Franco Maloberti
Favorite  |  View/Download:16/0  |  Submit date:2018/10/30
Sigma-delta Modulation  Modulators  Software Radio  Radio Receivers  Circuit Simulation  Band-pass Filters  Table Lookup  Reconfigurable Mismatch-free Time-interleaved Bandpass Sigma-delta Modulator  Wireless Communications  Control Parameters  Look-up Table  Path Numbers  Path Sampling Frequencies  Tuning Coefficients  Design Reconfigurability  Multiband Receiver  Software Defined Radio Systems  Behavioural Simulations  
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC with Partial Vcm-Based Switching Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017,Volume: 25,Issue: 3,Page: 1168-1172
Authors:  Dezhi Xing;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Fan Ye;  Junyan Ren;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:14/0  |  Submit date:2019/02/11
Common Mode Variation  Partial Vcm-based Switching  Time-interleaved Successive ApproximaTion Register Analog-to-digital Converter (Ti Sar Adc)  
DCM operation analysis of 3-level boost converters Journal article
ELECTRONICS LETTERS, 2017,Volume: 53,Issue: 4,Page: 270-272
Authors:  Yi-Wei Tan;  Chi-Seng Lam;  Sai-Weng Sin;  Man-Chung Wong;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:20/0  |  Submit date:2018/10/30
A High DR Multi-Channel Stage-Shared Hybrid Front-End for Integrated Power Electronics Controller Conference paper
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), Toyama, JAPAN, 7-9 Nov. 2016
Authors:  Yuan Ren;  Sai-Weng Sin;  Chi-Seng Lam;  Man-Chung Wong;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:12/0  |  Submit date:2018/12/23
Multi-channel Sigma Delta Front-end Interface  Programmable-gain  Integrated Pe Controller  
Active-Passive Delta Sigma Modulator for High-Resolution and Low-Power Applications Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017,Volume: 25,Issue: 1,Page: 364-374
Authors:  Hussain, Arshad;  Sin, Sai-Weng;  Chan, Chi-Hang;  U, Seng-Pan (Ben);  Maloberti, Franco;  Martins, Rui P.
Favorite  |  View/Download:20/0  |  Submit date:2018/10/30
Delta-Sigma Modulator (Delta Sigma m)  Discrete Time (Dt)  Low-gain-amplifier-based Switched-capacitor (Sc) Integrator  Noise Shaping  Passive Sc Integrator  
A 4x time-domain interpolation 6-bit 3.4 Gs/s 12.6 mw flash ADC in 65 nm CMOS Journal article
Journal of Semiconductor Technology and Science, 2016,Volume: 16,Issue: 4,Page: 395-404
Authors:  Jianwei Liu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
4x Time-domain Interpolation  Flash Adc  Sr-latch  Time Comparator  
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 2,Page: 365-377
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan (Ben) U;  Rui Paulo Martins
Favorite  |  View/Download:10/0  |  Submit date:2019/02/11
Analog-to-digital Conversion  Interleaving  Interpolation  Multibit/cycle Sar  Offset Calibration