UM
(Note: the search results are based on claimed items)

Browse/Search Results:  1-5 of 5 Help

Filters        
Selected(0)Clear Items/Page:    Sort:
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download:30/0  |  Submit date:2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 3,Page: 572-583
Authors:  Qiu, Lei;  Tang, Kai;  Zheng, Yuanjin;  Siek, Liter;  Zhu, Yan;  U, Seng-Pan
Favorite  |  View/Download:16/0  |  Submit date:2018/10/30
Digital Background Calibration  Subradix-2  Successive Pproximation Register (Sar) Analog-to-digital Converters (Adcs)  Time Interleaved (Ti)  Time Skew  
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017,Volume: 52,Issue: 10,Page: 2576-2588
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Li, Cheng;  Zhang, Wai-Hong;  Ho, Iok-Meng;  Wei, Lai;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download:18/0  |  Submit date:2018/10/30
Reference Buffer  Reference Error Calibration  Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Threshold Reconfigurable Comparator  
A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration Conference paper
2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings, Toyama, JAPAN, NOV 07-09, 2016
Authors:  Qiu L.;  Kai T.;  Zhu Y.;  Siek L.;  Zheng Y.;  Seng-Pan U.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/14
Sar Adcs  Time Skew Calibration  Time-interleaved  
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016,Volume: 24,Issue: 7,Page: 2603-2607
Authors:  Jianwei Liu;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo da Silva Martins
Favorite  |  View/Download:15/0  |  Submit date:2019/02/14
Background Linearity Calibration  Splitdigital- To-analog Converter (Dac)  Successive Approximation Register (Sar) Adc  Uniform Quantization Theory (Uqt)