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Split-based time-interleaved ADC with digital background timing-skew calibration Conference paper
2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Giardini Naxos, Italy, JUN 12-15, 2017
Authors:  Guo M.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:13/0  |  Submit date:2019/02/11
Adc  Converters  Digital Background Calibration  Split-adc  Time-interleaving  Timing  
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016,Volume: 24,Issue: 7,Page: 2603-2607
Authors:  Jianwei Liu;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo da Silva Martins
Favorite  |  View/Download:15/0  |  Submit date:2019/02/14
Background Linearity Calibration  Splitdigital- To-analog Converter (Dac)  Successive Approximation Register (Sar) Adc  Uniform Quantization Theory (Uqt)  
A 13-bit 60MS/s split pipelined ADC with background gain and mismatch error calibration Conference paper
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore, Singapore, 11-13 Nov. 2013
Authors:  Li Ding;  Wenlan Wu;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
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A background gain-calibration technique for low voltage pipelined ADCs based on nonlinear interpolation Conference paper
2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, OH, USA, 4-7 Aug. 2013
Authors:  Li Ding;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
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Digital Calibration  Lms Algorithm  Nonlinear Interpolation  Pipelined Adcs  
A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique Conference paper
2012 Proceedings of the ESSCIRC (ESSCIRC), Bordeaux, France, 17-21 Sept. 2012
Authors:  Rui Wang;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Zhihua Wang;  Rui Paulo Martins
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
Sar Adc  Pipelined  Digital Calibration  Op-amp Sharing  
A nonlinearity digital background calibration algorithm for 2.5bit/stage pipelined ADCs with opamp sharing architecture Conference paper
Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, Macau, China, 6-7 Oct. 2011
Authors:  Fei Y.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
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A charge pump based timing-skew calibration for time-interleaved ADC Conference paper
Midwest Symposium on Circuits and Systems, Yonsei Univ, Seoul, SOUTH KOREA, AUG 07-10, 2011
Authors:  Zhang P.;  Chen Z.;  Wei H.-G.;  Sin S.-W.;  Seng-Pan U.;  Wang Z.;  Martins R.P.
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Adc  Calibration  Charge Pump  Time-interleaved (Ti)  Timing Skew  
A digital background nonlinearity calibration algorithm for pipelined ADCs Conference paper
PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, Shanghai, China, 22-24 Sept. 2010
Authors:  Fei Y.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite  |  View/Download:4/0  |  Submit date:2019/02/11
A background amplifier offset calibration technique for high-resolution pipelined ADCs Conference paper
Proceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010, Montreal, QC, Canada, 20-23 June 2010
Authors:  Ding L.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite  |  View/Download:4/0  |  Submit date:2019/02/11