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A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current Conference paper
Authors:  Mao, Jiaji;  Guo, Mingqiang;  Sin, Sai-Weng;  Martins, Rui Paulo
Favorite  |  View/Download:18/0  |  Submit date:2018/10/30
Analog-to-digital conversion  digital background calibration  pipelined ADC  split ADC  opamp-sharing technique  
A 0.4 v 6.4 μw 3.3 MHz CMOS Bootstrapped Relaxation Oscillator with ±0.71% Frequency Deviation over -30 to 100 °c for Wearable and Sensing Applications Conference paper
Proceedings - IEEE International Symposium on Circuits and Systems
Authors:  Lei K.-M.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:12/0  |  Submit date:2019/02/11
bootstrap  bulk-driven amplifier  CMOS  relaxation oscillator (RxO)  ultra-low-voltage (ULV)  wearable devices  
Split-based time-interleaved ADC with digital background timing-skew calibration Conference paper
2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Giardini Naxos, Italy, JUN 12-15, 2017
Authors:  Guo M.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:14/0  |  Submit date:2019/02/11
Adc  Converters  Digital Background Calibration  Split-adc  Time-interleaving  Timing  
A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration Conference paper
2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings, Toyama, JAPAN, NOV 07-09, 2016
Authors:  Qiu L.;  Kai T.;  Zhu Y.;  Siek L.;  Zheng Y.;  Seng-Pan U.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/14
Sar Adcs  Time Skew Calibration  Time-interleaved  
A 13-bit 60MS/s split pipelined ADC with background gain and mismatch error calibration Conference paper
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore, Singapore, 11-13 Nov. 2013
Authors:  Li Ding;  Wenlan Wu;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:7/0  |  Submit date:2019/02/11
A background gain-calibration technique for low voltage pipelined ADCs based on nonlinear interpolation Conference paper
2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, OH, USA, 4-7 Aug. 2013
Authors:  Li Ding;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:7/0  |  Submit date:2019/02/11
Digital Calibration  Lms Algorithm  Nonlinear Interpolation  Pipelined Adcs  
A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique Conference paper
2012 Proceedings of the ESSCIRC (ESSCIRC), Bordeaux, France, 17-21 Sept. 2012
Authors:  Rui Wang;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Zhihua Wang;  Rui Paulo Martins
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
Sar Adc  Pipelined  Digital Calibration  Op-amp Sharing  
A nonlinearity digital background calibration algorithm for 2.5bit/stage pipelined ADCs with opamp sharing architecture Conference paper
Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, Macau, China, 6-7 Oct. 2011
Authors:  Fei Y.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
A charge pump based timing-skew calibration for time-interleaved ADC Conference paper
Midwest Symposium on Circuits and Systems, Yonsei Univ, Seoul, SOUTH KOREA, AUG 07-10, 2011
Authors:  Zhang P.;  Chen Z.;  Wei H.-G.;  Sin S.-W.;  Seng-Pan U.;  Wang Z.;  Martins R.P.
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
Adc  Calibration  Charge Pump  Time-interleaved (Ti)  Timing Skew  
A digital background nonlinearity calibration algorithm for pipelined ADCs Conference paper
PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, Shanghai, China, 22-24 Sept. 2010
Authors:  Fei Y.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite  |  View/Download:4/0  |  Submit date:2019/02/11