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A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Delta Sigma Modulator With Multirate Opamp Sharing Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 10,Page: 2641-2654
Authors:  Liang Qi;  Sai-Weng Sin;  Seng-Pan, U.;  Franco Maloberti;  Rui Paulo Martins
Favorite  |  View/Download:14/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Discrete-time (Dt) Delta Sigma (Delta Sigma) Modulator  Multi-stage Noise Shaping (Mash)  Wideband  Power-efficient  Opamp Sharing  Multirate  Successive Approximation Register (Sar) Quantizer  
A nonlinearity digital background calibration algorithm for 2.5bit/stage pipelined ADCs with opamp sharing architecture Conference paper
Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, Macau, China, 6-7 Oct. 2011
Authors:  Fei Y.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11