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1.2-V, 10-bit, 60– 360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 mm CMOS with minimised supply headroom Journal article
IET Circuits, Devices & Systems, 2010,Volume: 4,Issue: 1,Page: 1-13
Authors:  S.-W. Sin;  Seng-Pan U;  R.P. Martins
Favorite  |  View/Download:2/0  |  Submit date:2019/02/27
A 1.2-V 10-bit 60–360MS/s Time-Interleaved Pipelined ADC in 0.18μm CMOS with Minimized Supply Headroom Journal article
IET Circuits, Devices & Systems, 2010,Volume: 4,Issue: 1,Page: 1-13
Authors:  S.-W. Sin;  Seng-Pan U;  R.P. Martins
Favorite  |  View/Download:1/0  |  Submit date:2019/03/14
High performance multirate SC circuits with predictive correlated double sampling technique Journal article
Proceedings - IEEE International Symposium on Circuits and Systems, 1999,Volume: 2
Authors:  U Seng-Pan;  Martins R.P.;  Franca J.E.
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11