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A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration Conference paper
2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 5-9 Feb. 2017
Authors:  Chi-Hang Chan;  Yan Zhu;  Iok-Meng Ho;  Wai-Hong Zhang;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:17/0  |  Submit date:2018/11/06
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 2,Page: 365-377
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan (Ben) U;  Rui Paulo Martins
Favorite  |  View/Download:14/0  |  Submit date:2019/02/11
Analog-to-digital Conversion  Interleaving  Interpolation  Multibit/cycle Sar  Offset Calibration  
A power effective 5-bit 600 MS/s binary-search ADC with simplified switching Conference paper
Midwest Symposium on Circuits and Systems, Seattle, WA, AUG 01-04, 2010
Authors:  Wong S.S.;  Chio U.-F.;  Choi H.-L.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:10/0  |  Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Asynchronous Binary-search Adc  
Comparator-based successive folding ADC Conference paper
1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009, Shanghai, PEOPLES R CHINA, NOV 19-21, 2009
Authors:  Chio U.-F.;  Choi H.-L.;  Chan C.-H.;  Wong S.-S.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite  |  View/Download:7/0  |  Submit date:2019/02/11