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Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC with Partial Vcm-Based Switching Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017,Volume: 25,Issue: 3,Page: 1168-1172
Authors:  Dezhi Xing;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Fan Ye;  Junyan Ren;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:20/0  |  Submit date:2019/02/11
Common Mode Variation  Partial Vcm-based Switching  Time-interleaved Successive ApproximaTion Register Analog-to-digital Converter (Ti Sar Adc)  
Metastablility in SAR ADCs Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2017,Volume: 64,Issue: 2,Page: 111-115
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Boris Murmann;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:17/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Comparator  Metastability  Successive Approximation Register (Sar)  
Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2015,Volume: 62,Issue: 9,Page: 2196-2206
Authors:  Jianyu Zhong;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
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Analog-to-digital Converter (Adc)  Reference Noise  Successive-approximation-register (Sar) Adc  Thermal Noise  
Analog to digital converter circuit Patent
专利类型: 发明专利, 专利号: US8659461B1, 申请日期: 2012-11-13, 公开日期: 2014-02-25
Authors:  Yan Zhu;  Chi Hang Chan;  Sai Weng Sin;  Seng Pan U;  Rui Paulo da Silva Martins;  Franco Maloberti
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Split-SAR ADCs: Improved linearity with power and speed optimization Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014,Volume: 22,Issue: 2,Page: 372-383
Authors:  Yan Zhu;  Chi-Hang Chan;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins;  Franco Maloberti
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Linearity Analysis  Linearity Calibration  Sar Adcs  Split Dac  Vcm-based Switching  
A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 20-24 Feb. 2011
Authors:  Wei H.;  Chan C.-H.;  Chio U.-F.;  Sin S.-W.;  Seng-Pan U.;  Martins R.;  Maloberti F.
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A 0.024mm28b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Authors:  Wei, Hegong;  Chan, Chi-Hang;  Chio, U.-Fat;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, Rui;  Maloberti, Franco
Favorite  |  View/Download:3/0  |  Submit date:2018/11/06
Parasitics nonlinearity cancellation technique for split DAC architecture by using capacitive charge-pump Conference paper
Midwest Symposium on Circuits and Systems, Seattle, WA, AUG 01-04, 2010
Authors:  Zhu Y.;  Chan C.-H.;  Chio U.-F.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
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A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs Conference paper
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, France, 30 May-2 June 2010
Authors:  Zhu Y.;  Chan C.-H.;  Chio U.-F.;  Sin S.-W.;  U S.-P.;  Martins R.P.
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A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs Conference paper
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, Macao, PEOPLES R CHINA, NOV 30-DEC 03, 2008
Authors:  Chio U.-F.;  Wei H.-G.;  Zhu Y.;  Sin S.-W.;  Seng-Pan U.;  RPMartins
Favorite  |  View/Download:7/0  |  Submit date:2019/02/14