UM

Browse/Search Results:  1-2 of 2 Help

Filters        
Selected(0)Clear Items/Page:    Sort:
A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017,Volume: 64,Issue: 7,Page: 1684-1695
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:14/0  |  Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Low Power  Successive Approximation Architecture  Switched-capacitor Circuits  
A CMOS Delta-Sigma PLL Transmitter with Efficient Modulation Bandwidth Calibration Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2015,Volume: 62,Issue: 7,Page: 1716-1725
Authors:  Huang M.;  Chen D.;  Guo J.;  Ye H.;  Xu K.;  Liang X.;  Lu Y.
Favorite  |  View/Download:9/0  |  Submit date:2019/02/14
Delta-sigma Phase Locked Loop (Pll)  Modulation Bandwidth Calibration  Transmitters