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A hardware-efficient feedback polynomial topology for dpd linearization of power amplifiers: Theory and FPGA validation Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 9,Page: 2889-2902
Authors:  Cheang C.-F.;  Mak P.-I.;  Martins R.P.
Favorite | View/Download:6/0 | TC[WOS]:3 TC[Scopus]:0 | Submit date:2019/02/11
Carrier-aggregation  Digital Predistortion (Dpd)  Field-programmable Gate Array (Fpga)  Identification  Power Amplifier (Pa)  Recursive Least Square (Rls)