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60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017,Volume: 52,Issue: 10,Page: 2576-2588
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Li, Cheng;  Zhang, Wai-Hong;  Ho, Iok-Meng;  Wei, Lai;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite | View/Download:33/0 | TC[WOS]:12 TC[Scopus]:0 | Submit date:2018/10/30
Reference Buffer  Reference Error Calibration  Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Threshold Reconfigurable Comparator  
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 2,Page: 365-377
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan (Ben) U;  Rui Paulo Martins
Favorite | View/Download:16/0 | TC[WOS]:9 TC[Scopus]:0 | Submit date:2019/02/11
Analog-to-digital Conversion  Interleaving  Interpolation  Multibit/cycle Sar  Offset Calibration  
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2010,Volume: 45,Issue: 6,Page: 1111-1121
Authors:  Yan Zhu;  Chi-Hang Chan;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins;  Franco Maloberti
Favorite | View/Download:118/0 | TC[WOS]:367 TC[Scopus]:0 | Submit date:2018/10/30
Charge-recovery  Reference-free  Switched Technique