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60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017,Volume: 52,Issue: 10,Page: 2576-2588
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Li, Cheng;  Zhang, Wai-Hong;  Ho, Iok-Meng;  Wei, Lai;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download:26/0  |  Submit date:2018/10/30
Reference Buffer  Reference Error Calibration  Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Threshold Reconfigurable Comparator  
A 0.011mm2 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages Conference paper
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), Toyama, JAPAN, 7-9 Nov. 2016
Authors:  Chi-Hang Chan;  Yan Zhu;  Iok-Meng Ho;  Wai-Hong Zhang;  Chon-Lam Lio;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:16/0  |  Submit date:2019/02/11
A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction Conference paper
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, 12-15 Sept. 2016
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:16/0  |  Submit date:2019/02/11
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 2,Page: 365-377
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan (Ben) U;  Rui Paulo Martins
Favorite  |  View/Download:14/0  |  Submit date:2019/02/11
Analog-to-digital Conversion  Interleaving  Interpolation  Multibit/cycle Sar  Offset Calibration  
A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS Conference paper
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, PEOPLES R CHINA, MAY 19-23, 2013
Authors:  Wen-Lan Wu;  Yan Zhu;  Li Ding;  Chi-Hang Chan;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:12/0  |  Submit date:2019/02/11
N-bits successive approximation register analog-to-digital converting circuit Patent
专利类型: 发明专利, 专利号: US20120306679A1, 申请日期: 2011-06-01,
Authors:  Yan ZHU;  Chi-Hang CHAN;  U-Fat CHIO;  Sai-Weng SIN;  Seng-Pan U;  Rui Paulo Da Silva MARTINS;  Franco MALOBERTI
Favorite  |  View/Download:12/0  |  Submit date:2019/02/26
N-Bits Successive Approximation Register Analog-to-Digital Converter Circuit Patent
专利类型: 发明专利, 专利号: US8344931B2, 申请日期: 2011-06-01,
Authors:  Yan Zhu;  Chi-Hang CHAN;  U-Fat CHIO;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo da Silva Martins;  Franco Maloberti
Favorite  |  View/Download:5/0  |  Submit date:2019/03/06
N-bits successive approximation register analog-to-digital converting circuit Patent
专利类型: 发明专利, 专利号: US8344931B2, 申请日期: 2011-06-01, 公开日期: 2013
Authors:  Yan Zhu;  Chi Hang Chan;  U Fat Chio;  Sai Weng Sin;;  Seng Pan U;  Rui Paulo Da Silva Martins;  Franco Maloberti
Favorite  |  View/Download:3/0  |  Submit date:2020/06/04