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A 0.011mm2 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages Conference paper
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), Toyama, JAPAN, 7-9 Nov. 2016
Authors:  Chi-Hang Chan;  Yan Zhu;  Iok-Meng Ho;  Wai-Hong Zhang;  Chon-Lam Lio;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:16/0  |  Submit date:2019/02/11
A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction Conference paper
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, 12-15 Sept. 2016
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:16/0  |  Submit date:2019/02/11
A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS Conference paper
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, PEOPLES R CHINA, MAY 19-23, 2013
Authors:  Wen-Lan Wu;  Yan Zhu;  Li Ding;  Chi-Hang Chan;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:12/0  |  Submit date:2019/02/11