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Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 11,Page: 2279-2289
Authors:  Wang, Guan Cheng;  Zhu, Yan;  Chan, Chi-Hang;  Seng-Pan, U.;  Martins, Rui P.
Favorite  |  View/Download:14/0  |  Submit date:2019/01/17
Bridge digital-to-analog converter (DAC)  gain error calibration  successive approximation register (SAR)  analog-to-digital converters (ADCs)  testing signal generation (TSG)  
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 3,Page: 572-583
Authors:  Qiu, Lei;  Tang, Kai;  Zheng, Yuanjin;  Siek, Liter;  Zhu, Yan;  U, Seng-Pan
Favorite  |  View/Download:24/0  |  Submit date:2018/10/30
Digital Background Calibration  Subradix-2  Successive Pproximation Register (Sar) Analog-to-digital Converters (Adcs)  Time Interleaved (Ti)  Time Skew  
Passive Noise Shaping in SAR ADC With Improved Efficiency Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 2,Page: 416-420
Authors:  Song, Yan;  Chan, Chi-Hang;  Zhu, Yan;  Geng, Li;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download:26/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Delta Sampling  Oversampling  Passive Noise Shaping (Pns)  Successive Approximation Register (Sar)