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A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 10,Page: 3196-3206
Authors:  Kong L.;  Chen Y.;  Boon C.C.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
Automatic Gain Control (Agc) Amplifier  Bipolar Junction Transistors (Bjts)  Cmos  Db-linear  Dynamic Range  Negative Exponential Generator (Neg)  Pseudo-exponential Function  Rational Approximation  Taylor Series  
A hardware-efficient feedback polynomial topology for dpd linearization of power amplifiers: Theory and FPGA validation Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 9,Page: 2889-2902
Authors:  Cheang C.-F.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:3/0  |  Submit date:2019/02/11
Carrier-aggregation  Digital Predistortion (Dpd)  Field-programmable Gate Array (Fpga)  Identification  Power Amplifier (Pa)  Recursive Least Square (Rls)  
A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 9,Page: 3014-3026
Authors:  Chen Y.;  Mak P.-I.;  Boon C.C.;  Martins R.P.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
Bandwidth (Bw)  Cmos  Cross-quadrature Clocking  D-type Flip-flop (Dff)  Data-dependent Jitter (Ddj)  Duobinary  Figure-of-merit (Fom)  Latch  Multi-level Signaling  Multiplexer (Mux)  Selector  Timing Margin