UM

Browse/Search Results:  1-3 of 3 Help

Filters                    
Selected(0)Clear Items/Page:    Sort:
A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction Conference paper
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, 12-15 Sept. 2016
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:17/0  |  Submit date:2019/02/11
Switching-loss reduction technique in active power filters without auxiliary circuits Journal article
IET Power Electronics, 2016,Volume: 9,Issue: 4,Page: 728-742
Authors:  Chi-Seng Lam;  Man-Chung Wong;  Ning-Yi Dai;  Wai-Hei Choi;  Xiao-Xi Cui;  Chi-Yung Chung
Favorite  |  View/Download:10/0  |  Submit date:2018/12/23
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 2,Page: 365-377
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan (Ben) U;  Rui Paulo Martins
Favorite  |  View/Download:14/0  |  Submit date:2019/02/11
Analog-to-digital Conversion  Interleaving  Interpolation  Multibit/cycle Sar  Offset Calibration