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Source Publication:IEEE Journal of Solid-State Circuits
Document Type:期刊论文
Indexed By:SCI
Community:微電子研究院
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An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS
Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 5,Page: 1223-1234
Authors:
Yan Zhu
;
Chi-Hang Chan
;
Seng-Pan U
;
Rui Paulo Martins
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Submit date:2019/02/11
Offset Calibration
Pipelined-successive Approximation Register (Sar) Analog-to-digital Converter (Adc)
Sar Logic