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Design Considerations of Distributed and Centralized Switched-Capacitor Converters for Power Supply On-Chip Journal article
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, 2018,Volume: 6,Issue: 2,Page: 515-525
Authors:  Lu, Yan;  Jiang, Junmin;  Ki, Wing-Hung
Favorite  |  View/Download:16/0  |  Submit date:2018/10/30
Active-matrix Light-emitting Diode (Amled)  Amplifier  Charge Pump  Converter Ring  Dc-dc Converter  Digital Control  Dynamic Voltage Scaling (Dvs)  Fully Integrated Voltage Regulator (Fivr)  Hybrid Converter  Low-dropout Regulator (Ldo)  Multilevel  Multiphase  Resonant Converter  Switched-capacitor (Sc) Power Converter  Voltage-controlled Oscillator (Vco)  
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download:31/0  |  Submit date:2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 8,Page: 1966-1976
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, Rui P.;  Maloberti, Franco
Favorite  |  View/Download:27/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Flash  Time-based Dual-edge-triggered  
A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017,Volume: 64,Issue: 7,Page: 1684-1695
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:14/0  |  Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Low Power  Successive Approximation Architecture  Switched-capacitor Circuits  
A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration Conference paper
2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 5-9 Feb. 2017
Authors:  Chi-Hang Chan;  Yan Zhu;  Iok-Meng Ho;  Wai-Hong Zhang;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:15/0  |  Submit date:2018/11/06
A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration Conference paper
2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings, Toyama, JAPAN, NOV 07-09, 2016
Authors:  Qiu L.;  Kai T.;  Zhu Y.;  Siek L.;  Zheng Y.;  Seng-Pan U.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/14
Sar Adcs  Time Skew Calibration  Time-interleaved  
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017,Volume: 25,Issue: 1,Page: 354-363
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Pan, Seng U.;  Martins, Rui Paulo
Favorite  |  View/Download:15/0  |  Submit date:2018/10/30
Offset Calibration  Partial Interleaving (Pi)  Pipelined-sar  Stage-gain Error Calibration  
A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction Conference paper
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, 12-15 Sept. 2016
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:14/0  |  Submit date:2019/02/11
An NMOS-LDO Regulated Switched-Capacitor DC-DC Converter with Fast-Response Adaptive-Phase Digital Control Journal article
IEEE Transactions on Power Electronics, 2016,Volume: 31,Issue: 2,Page: 1294-1303
Authors:  Lu Y.;  Ki W.-H.;  Patrick Yue C.
Favorite  |  View/Download:11/0  |  Submit date:2019/02/14
Dc-dc Converter  Digital Controller  Low Dropout Regulator (Ldo)  Power Supply Rejection (Psr)  Switched Capacitor Power Converter (Scpc)  Voltage Regulator  
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 2,Page: 365-377
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan (Ben) U;  Rui Paulo Martins
Favorite  |  View/Download:10/0  |  Submit date:2019/02/11
Analog-to-digital Conversion  Interleaving  Interpolation  Multibit/cycle Sar  Offset Calibration