Selected(0)Clear
Items/Page: Sort: |
| Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 2,Page: 481-485 Authors: Liu J.; Chan C.-H.; Sin S.-W.; Seng-Pan U. ; Martins R.P.
 Favorite | View/Download:42/0 | TC[WOS]:2 TC[Scopus]:2 | Submit date:2019/02/13 Bandwidth mismatches split-digital to analog converter (DAC) successive-approximation-register (SAR) analog-to-digital converter (ADC) time-interleaved (TI) variance based window detector (WD) |
| Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 2,Page: 489-501 Authors: Xing D.; Zhu Y.; Chan C.-H.; Maloberti F.; Seng-Pan U. ; Martins R.P.
 Favorite | View/Download:25/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11 reference interference SAR ADC time-interleaved scheme two-step SAR conversion |
| An Integrated DC-DC Converter with Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery Conference paper 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings Authors: Chio U.-F.; Wen K.-C.; Sin S.-W.; Lam C.-S.; Lu Y.; Maloberti F.; Martins R.P.
 Favorite | View/Download:57/0 | TC[WOS]:0 TC[Scopus]:1 | Submit date:2019/02/11 fully integrated SC DC-DC converter switched-capacitor voltage-controlled oscillator (VCO) |
| An 11b 1GS/s Time-Interleaved ADC with Linearity Enhanced T/H Conference paper 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings Authors: Zhu Y.; Chan C.-H.; Martins R.P.
 Favorite | View/Download:7/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11 |
| A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler Conference paper 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings Authors: Jiang W.; Zhu Y.; Chan C.-H.; Murmann B.; Seng-Pan U. ; Martins R.P.
 Favorite | View/Download:14/0 | TC[WOS]:0 TC[Scopus]:3 | Submit date:2019/02/11 background calibration current integrating sampler Time-interleaved ADC timing skew |
| A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS Journal article IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018,Volume: 65,Issue: 11,Page: 1534-1538 Authors: Wang, X. Shawn; Jin, Xin; Du, Jieqiong; Li, Yilei; Du, Yuan; Wong, Chien-Heng; Kuan, Yen-Cheng; Chan, Chi-Hang; Chang, Mau-Chung Frank
 Favorite | View/Download:11/0 | TC[WOS]:3 TC[Scopus]:3 | Submit date:2019/01/17 Analog-to-digital converter (ADC) virtual-ground sampling SAR time-interleaved |
| A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS Journal article IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3606-3616 Authors: Zhu Y.; Chan C.-H.; Zheng Z.-H.; Li C.; Zhong J.-Y.; Martins R.P.
 Favorite | View/Download:12/0 | TC[WOS]:4 TC[Scopus]:4 | Submit date:2019/02/11 passive sharing pipelined-SAR ADC sampling front-end design switch bootstrap technique Time-interleaved ADC |
| A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS Conference paper Authors: Zhu, Yan; Chan, Chi-Hang; Zheng, Zi-Hao; Li, Cheng; Zhong, Jian-Yu; Martins, Rui P.
 Favorite | View/Download:50/0 | TC[WOS]:4 TC[Scopus]:4 | Submit date:2018/10/30 Time-interleaved ADC sampling front-end design passive sharing pipelined-SAR ADC switch bootstrap technique |
| A 39mW 7b 8GS/s 8-way TI ADC with Cross-linearized Input and Bootstrapped Sampling Buffer Front-end Conference paper ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference Authors: Chan C.-H.; Zhu Y.; Zheng Z.; Martins R.P.
 Favorite | View/Download:14/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11 |
| An 8.8-GS/s 8b time-interleaved SAR ADC with 50-dB SFDR using complementary dual-loop-assisted buffers in 28nm CMOS Conference paper Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium Authors: Wang X.S.; Chan C.-H.; Du J.; Wong C.-H.; Li Y.; Du Y.; Kuan Y.-C.; Hu B.; Chang M.-C.F.
 Favorite | View/Download:7/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/14 |