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| Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 2,Page: 489-501
作者: Xing D.; Zhu Y.; Chan C.-H.; Maloberti F.; Seng-Pan U.; Martins R.P.
  收藏 | 浏览/下载：5/0 | 提交时间：2019/02/11
reference interference SAR ADC time-interleaved scheme two-step SAR conversion |
| Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 2,Page: 481-485
作者: Liu J.; Chan C.-H.; Sin S.-W.; Seng-Pan U.; Martins R.P.
收藏 | 浏览/下载：15/0 | 提交时间：2019/02/13
Bandwidth mismatches split-digital to analog converter (DAC) successive-approximation-register (SAR) analog-to-digital converter (ADC) time-interleaved (TI) variance based window detector (WD) |
| An Integrated DC-DC Converter with Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery Conference paper
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
作者: Chio U.-F.; Wen K.-C.; Sin S.-W.; Lam C.-S.; Lu Y.; Maloberti F.; Martins R.P.
收藏 | 浏览/下载：2/0 | 提交时间：2019/02/11
fully integrated SC DC-DC converter switched-capacitor voltage-controlled oscillator (VCO) |
| A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler Conference paper
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
作者: Jiang W.; Zhu Y.; Chan C.-H.; Murmann B.; Seng-Pan U.; Martins R.P.
收藏 | 浏览/下载：4/0 | 提交时间：2019/02/11
background calibration current integrating sampler Time-interleaved ADC timing skew |
| An 11b 1GS/s Time-Interleaved ADC with Linearity Enhanced T/H Conference paper
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
作者: Zhu Y.; Chan C.-H.; Martins R.P.
收藏 | 浏览/下载：3/0 | 提交时间：2019/02/11 |
| A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS Conference paper
作者: Zhu, Yan; Chan, Chi-Hang; Zheng, Zi-Hao; Li, Cheng; Zhong, Jian-Yu; Martins, Rui P.
收藏 | 浏览/下载：25/0 | 提交时间：2018/10/30
Time-interleaved ADC sampling front-end design passive sharing pipelined-SAR ADC switch bootstrap technique |
| A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018,Volume: 65,Issue: 11,Page: 1534-1538
作者: Wang, X. Shawn; Jin, Xin; Du, Jieqiong; Li, Yilei; Du, Yuan; Wong, Chien-Heng; Kuan, Yen-Cheng; Chan, Chi-Hang; Chang, Mau-Chung Frank
收藏 | 浏览/下载：3/0 | 提交时间：2019/01/17
Analog-to-digital converter (ADC) virtual-ground sampling SAR time-interleaved |
| A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3606-3616
作者: Zhu Y.; Chan C.-H.; Zheng Z.-H.; Li C.; Zhong J.-Y.; Martins R.P.
收藏 | 浏览/下载：2/0 | 提交时间：2019/02/11
passive sharing pipelined-SAR ADC sampling front-end design switch bootstrap technique Time-interleaved ADC |
| A 39mW 7b 8GS/s 8-way TI ADC with Cross-linearized Input and Bootstrapped Sampling Buffer Front-end Conference paper
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference
作者: Chan C.-H.; Zhu Y.; Zheng Z.; Martins R.P.
收藏 | 浏览/下载：4/0 | 提交时间：2019/02/11 |
| An 8.8-GS/s 8b time-interleaved SAR ADC with 50-dB SFDR using complementary dual-loop-assisted buffers in 28nm CMOS Conference paper
Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
作者: Wang X.S.; Chan C.-H.; Du J.; Wong C.-H.; Li Y.; Du Y.; Kuan Y.-C.; Hu B.; Chang M.-C.F.
收藏 | 浏览/下载：0/0 | 提交时间：2019/02/14 |
