×
验证码:
换一张
Forgotten Password?
Stay signed in
Login With UMPASS
English
|
繁體
Login With UMPASS
Log In
ALL
ORCID
Title
Creator
Date Issued
Subject Area
Keyword
Document Type
Source Publication
Date Accessioned
Indexed By
Publisher
Funding Project
MOST Discipline Catalogue
Study Hall
Image search
Paste the image URL
Home
Collections
Authors
DocType
Subjects
K-Map
Evaluation
K-Integration
News
Search in the results
Collection
INSTITUTE... [19]
Faculty o... [18]
Authors
ZHU YAN [17]
RUI PAULO... [15]
SIN SAI W... [15]
CHAN CHI ... [14]
U SENG PA... [13]
MAK PUI IN [1]
More...
Document Type
Journal a... [12]
Conference... [8]
论文 [3]
Patent [1]
Date Issued
2018 [3]
2017 [6]
2016 [4]
2015 [1]
2014 [2]
2011 [2]
More...
Language
英语 [23]
Source Publication
IEEE TRANS... [5]
IEEE Trans... [4]
Digest of ... [2]
IEEE Trans... [2]
2008 51ST ... [1]
2009 Inter... [1]
More...
Funding Project
Indexed By
SCI [19]
Funding Organization
×
Knowledge Map
UM
Start a Submission
Submissions
Unclaimed
Claimed
Attach Fulltext
Bookmarks
Browse/Search Results:
1-10 of 24
Help
Selected(
0
)
Clear
Items/Page:
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Sort:
Select
Issue Date Ascending
Issue Date Descending
Submit date Ascending
Submit date Descending
WOS Cited Times Ascending
WOS Cited Times Descending
Title Ascending
Title Descending
Author Ascending
Author Descending
Journal Impact Factor Ascending
Journal Impact Factor Descending
Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area
Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 11,Page: 2279-2289
Authors:
Wang, Guan Cheng
;
Zhu, Yan
;
Chan, Chi-Hang
;
Seng-Pan, U.
;
Martins, Rui P.
Favorite
|
View/Download:19/0
|
TC[WOS]:
0
TC[Scopus]:
1
|
Submit date:2019/01/17
Bridge digital-to-analog converter (DAC)
gain error calibration
successive approximation register (SAR)
analog-to-digital converters (ADCs)
testing signal generation (TSG)
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS
Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 3,Page: 572-583
Authors:
Qiu, Lei
;
Tang, Kai
;
Zheng, Yuanjin
;
Siek, Liter
;
Zhu, Yan
;
U, Seng-Pan
Favorite
|
View/Download:40/0
|
TC[WOS]:
3
TC[Scopus]:
5
|
Submit date:2018/10/30
Digital Background Calibration
Subradix-2
Successive Pproximation Register (Sar) Analog-to-digital Converters (Adcs)
Time Interleaved (Ti)
Time Skew
Passive Noise Shaping in SAR ADC With Improved Efficiency
Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 2,Page: 416-420
Authors:
Song, Yan
;
Chan, Chi-Hang
;
Zhu, Yan
;
Geng, Li
;
Seng-Pan, U.
;
Martins, Rui Paulo
Favorite
|
View/Download:41/0
|
TC[WOS]:
3
TC[Scopus]:
7
|
Submit date:2018/10/30
Analog-to-digital Converter (Adc)
Delta Sampling
Oversampling
Passive Noise Shaping (Pns)
Successive Approximation Register (Sar)
A 12b 180MS/s 0.068mm(2) With Full-Calibration-Integrated Pipelined-SAR ADC
Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 7,Page: 1684-1695
Authors:
Zhong, Jianyu
;
Zhu, Yan
;
Chan, Chi-Hang
;
Sin, Sai-Weng
;
U, Seng-Pan
;
Martins, Rui Paulo
Favorite
|
View/Download:29/0
|
TC[WOS]:
9
TC[Scopus]:
12
|
Submit date:2018/10/30
Analog-to-digital converter (ADC)
successive approximation architecture
low power
switched-capacitor circuits
A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC
Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017,Volume: 64,Issue: 7,Page: 1684-1695
Authors:
Jianyu Zhong
;
Yan Zhu
;
Chi-Hang Chan
;
Sai-Weng Sin
;
Seng-Pan U
;
Rui Paulo Martins
Favorite
|
View/Download:27/0
|
TC[WOS]:
9
TC[Scopus]:
12
|
Submit date:2019/02/11
Analog-to-digital Converter (Adc)
Low Power
Successive Approximation Architecture
Switched-capacitor Circuits
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial V-cm-Based Switching
Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017,Volume: 25,Issue: 3,Page: 1168-1172
Authors:
Xing, Dezhi
;
Zhu, Yan
;
Chan, Chi-Hang
;
Sin, Sai-Weng
;
Ye, Fan
;
Ren, Junyan
;
U, Seng-Pan
;
Martins, Rui Paulo
Favorite
|
View/Download:22/0
|
TC[WOS]:
5
TC[Scopus]:
8
|
Submit date:2018/10/30
Common mode variation
partial V-cm-based switching
time-interleaved successive approximation register analog-to-digital converter (TI SAR ADC)
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC with Partial Vcm-Based Switching
Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017,Volume: 25,Issue: 3,Page: 1168-1172
Authors:
Dezhi Xing
;
Yan Zhu
;
Chi-Hang Chan
;
Sai-Weng Sin
;
Fan Ye
;
Junyan Ren
;
Seng-Pan U
;
Rui Paulo Martins
Favorite
|
View/Download:33/0
|
TC[WOS]:
5
TC[Scopus]:
8
|
Submit date:2019/02/11
Common Mode Variation
Partial Vcm-based Switching
Time-interleaved Successive ApproximaTion Register Analog-to-digital Converter (Ti Sar Adc)
Metastablility in SAR ADCs
Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2017,Volume: 64,Issue: 2,Page: 111-115
Authors:
Chi-Hang Chan
;
Yan Zhu
;
Sai-Weng Sin
;
Boris Murmann
;
Seng-Pan U
;
R. P. Martins
Favorite
|
View/Download:29/0
|
TC[WOS]:
3
TC[Scopus]:
6
|
Submit date:2018/10/30
Analog-to-digital Converter (Adc)
Comparator
Metastability
Successive Approximation Register (Sar)
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations
Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017,Volume: 25,Issue: 1,Page: 354-363
Authors:
Zhu, Yan
;
Chan, Chi-Hang
;
Pan, Seng U.
;
Martins, Rui Paulo
Favorite
|
View/Download:30/0
|
TC[WOS]:
7
TC[Scopus]:
8
|
Submit date:2018/10/30
Offset Calibration
Partial Interleaving (Pi)
Pipelined-sar
Stage-gain Error Calibration
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC
Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016,Volume: 24,Issue: 7,Page: 2603-2607
Authors:
Jianwei Liu
;
Yan Zhu
;
Chi-Hang Chan
;
Sai-Weng Sin
;
Seng-Pan U
;
Rui Paulo da Silva Martins
Favorite
|
View/Download:30/0
|
TC[WOS]:
7
TC[Scopus]:
9
|
Submit date:2019/02/14
Background Linearity Calibration
Splitdigital- To-analog Converter (Dac)
Successive Approximation Register (Sar) Adc
Uniform Quantization Theory (Uqt)