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Analysis of common-mode interference and jitter of clock receiver circuits with improved topology Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 6,Page: 1819-1829
Authors:  Yang X.;  Zhu Y.;  Chan C.-H.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
Isf  Low Clock Jitter Circuit  Self-bias  
A High-Voltage-Enabled Class-D Polar PA Using Interactive AM-AM Modulation, Dynamic Matching, and Power-Gating for Average PAE Enhancement Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 11,Page: 2844-2857
Authors:  Yu, Wei-Han;  Peng, Xingqiang;  Mak, Pui-In;  Martins, Rui P.
Favorite  |  View/Download:11/0  |  Submit date:2018/10/30
AA Battery  antenna impedance mismatch  class-D  CMOS  digital AM modulation  dynamic matching network (DMN)  error-vector magnitude (EVM)  inverter chain  leakage current  matching network (MN)  polar  power amplifier (PA)  power-added efficiency (PAE)  power gating