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Understanding the Impact of Cu-In-Ga-S Nanoparticles Compactness on Holes Transfer of Perovskite Solar Cells Journal article
Nanomaterials, 2019,Volume: 9,Issue: 2,Page: 286
Authors:  Dandan Zhao;  Yinghui Wu;  Bao Tu;  Guichuan Xing;  Haifeng Li;  Zhubing He
Favorite  |  View/Download：3/0  |  Submit date：2019/04/29
Holes Transport Layer  Compactness  Hole Transfer  Recombination  Cu-in-ga-s  Perovskite Solar Cells  
27.3 A Piezoelectric Energy-Harvesting Interface Using Split Phase Flipping-Capacitor Rectifier and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3× Energy Extraction Improvement Conference paper
2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, USA, 17-21 Feb. 2019
Authors:  Zhiyuan Chen;  Yang Jiang;  Man-Kay Law;  Pui-In Mak;  Xiaoyang Zeng;  Rui P. Martins
Favorite  |  View/Download：37/0  |  Submit date：2019/03/13
Algorithmic Voltage-Feed-In Topology for Fully Integrated Fine-Grained Rational Buck-Boost Switched-Capacitor DC-DC Converters Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 12,Page: 3455-3469
Authors:  Jiang, Yang;  Law, Man-Kay;  Mak, Pui-In;  Martins, Rui P.
Favorite  |  View/Download：5/0  |  Submit date：2019/01/17
Algorithmic voltage-feed-in (AVFI) topology  buck-boost  dc-dc  linear topology  parasitic loss  power density  rational voltage conversion ratio  reconfigurable  reference-selective bootstrapping  switched capacitor  
A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems Conference paper
2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
Authors:  Mao F.;  Lu Y.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download：1/0  |  Submit date：2019/02/11
delay compensation  feedback loop  implantable medical devices  real time  voltage doubler  wireless power transfer  
A 4.06 mW 10-bit 150 MS/s SAR ADC With 1.5-bit/cycle Operation for Medical Imaging Applications Journal article
IEEE SENSORS JOURNAL, 2018,Volume: 18,Issue: 11,Page: 4553-4560
Authors:  Sunny, Sharma;  Chen, Yong;  Boon, Chirn Chye
Favorite  |  View/Download：8/0  |  Submit date：2018/10/30
1.5-bit/cycle  ADC  capacitive digital-to-analog converter (CDAC)  CMOS  error correction  low power  medical imaging  redundancy  SAR  successive approximation register  
A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle Operation for Medical Imaging Applications Journal article
IEEE Sensors Journal, 2018,Volume: 18,Issue: 11,Page: 4553-4560
Authors:  Sunny S.;  Chen Y.;  Boon C.C.
Favorite  |  View/Download：1/0  |  Submit date：2019/02/14
1.5-bit/cycle  ADC  capacitive digital-to-analog converter (CDAC)  CMOS  error correction  low power  medical imaging  redundancy  SAR  successive approximation register  
A 0.032-mm2 0.15-V Three-Stage Charge-Pump Scheme Using a Differential Bootstrapped Ring-VCO for Energy-Harvesting Applications Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2018,Volume: 65,Issue: 2,Page: 146-150
Authors:  Yi H.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download：8/0  |  Submit date：2019/02/11
Bootstrapped  Charge Pump (Cp)  Cmos  Energy Harvesting  Reverse Current  Ring-vco  Ultra-low Voltage  
A 0.22-to-2.4V-input fine-grained fully integrated rational buck-boost SC DC-DC converter using algorithmic voltage-feed-in (AVFI) topology achieving 84.1% peak efficiency at 13.2mW/mm2 Conference paper
2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, 11-15 Feb. 2018
Authors:  Yang Jiang;  Man-Kay Law;  Pui-In Mak;  Rui P. Martins
Favorite  |  View/Download：7/0  |  Submit date：2018/11/06
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017,Volume: 52,Issue: 10,Page: 2576-2588
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Li, Cheng;  Zhang, Wai-Hong;  Ho, Iok-Meng;  Wei, Lai;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download：16/0  |  Submit date：2018/10/30
Reference Buffer  Reference Error Calibration  Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Threshold Reconfigurable Comparator  
A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 8,Page: 1966-1976
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, Rui P.;  Maloberti, Franco
Favorite  |  View/Download：22/0  |  Submit date：2018/10/30
Analog-to-digital Converter (Adc)  Flash  Time-based Dual-edge-triggered