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An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC with <1.5-ps Uncalibrated Quantization Steps Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 12,Page: 3225-3235
Authors:  Zhang,Minglei;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite | View/Download:0/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/04
Analog-to-digital converter (ADC)  and temperature (PVT) robustness  high-speed ADC  metastability  process  supply voltage  time interpolation  time residue  time-domain ADC  time-to-digital converter (TDC)  
Piezoelectric energy-harvesting interface using split-phase flipping-capacitor rectifier with capacitor reuse for input power adaptation Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 8,Page: 2106-2117
Authors:  Chen,Zhiyuan;  Law,Man Kay;  Mak,Pui In;  Zeng,Xiaoyang;  Martins,Rui P.
Favorite | View/Download:0/0 | TC[WOS]:1 TC[Scopus]:2 | Submit date:2021/03/04
Capacitor reuse  maximum output power improving rate (MOPIR)  multiple-voltage-conversion ratio (MVCR)  piezoelectric energy harvesting (PEH)  split-phase flipping-capacitor rectifier (SPFCR)  switched-capacitor dc-dc converter  
A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC Journal article
IEEE Journal of Solid-State Circuits, 2020
Authors:  Song,Yan;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite | View/Download:0/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/09
Analog-to-digital converter (ADC)  Calibration  Capacitors  Gain  noise-shaping (NS)  offset calibration  Pipelines  Registers  successive approximation register (SAR)-assisted pipeline  System-on-chip  time interleaving.  Transfer functions  
A Hybrid Boost Converter With Cross-Connected Flying Capacitors Journal article
IEEE Journal of Solid-State Circuits, 2020
Authors:  Huang,Mo;  Lu,Yan;  Hu,Tingxu;  Martins,Rui P.
Favorite | View/Download:0/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/09
Boost converter  bootstrap  Capacitors  dc-dc converter  high conversion ratio (CR)  Inductors  Logic gates  multi-phase  soft-charging.  Steady-state  Stress  Switches  Topology  
Algebraic Series-Parallel-Based Switched-Capacitor DC-DC Boost Converter with Wide Input Voltage Range and Enhanced Power Density Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 11,Page: 3118-3134
Authors:  Jiang,Yang;  Law,Man Kay;  Chen,Zhiyuan;  Mak,Pui In;  Martins,Rui P.
Favorite | View/Download:0/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/09
Algebraic  boost converter  charge sharing loss  DC-DC  parasitic loss  power density  rational  series-parallel (SP)  switched-capacitor (SC)  voltage conversion ratio (VCR)  
27.3 A Piezoelectric Energy-Harvesting Interface Using Split Phase Flipping-Capacitor Rectifier and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3× Energy Extraction Improvement Conference paper
2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, USA, 17-21 Feb. 2019
Authors:  Zhiyuan Chen;  Yang Jiang;  Man-Kay Law;  Pui-In Mak;  Xiaoyang Zeng;  Rui P. Martins
Favorite | View/Download:84/0 | TC[WOS]:0 TC[Scopus]:8 | Submit date:2019/03/13
Understanding the Impact of Cu-In-Ga-S Nanoparticles Compactness on Holes Transfer of Perovskite Solar Cells Journal article
Nanomaterials, 2019,Volume: 9,Issue: 2,Page: 286
Authors:  Dandan Zhao;  Yinghui Wu;  Bao Tu;  Guichuan Xing;  Haifeng Li;  Zhubing He
Favorite | View/Download:23/0 | TC[WOS]:4 TC[Scopus]:3 | Submit date:2019/04/29
Holes Transport Layer  Compactness  Hole Transfer  Recombination  Cu-in-ga-s  Perovskite Solar Cells  
Algorithmic Voltage-Feed-In Topology for Fully Integrated Fine-Grained Rational Buck-Boost Switched-Capacitor DC-DC Converters Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 12,Page: 3455-3469
Authors:  Jiang, Yang;  Law, Man-Kay;  Mak, Pui-In;  Martins, Rui P.
Favorite | View/Download:19/0 | TC[WOS]:6 TC[Scopus]:6 | Submit date:2019/01/17
Algorithmic voltage-feed-in (AVFI) topology  buck-boost  dc-dc  linear topology  parasitic loss  power density  rational voltage conversion ratio  reconfigurable  reference-selective bootstrapping  switched capacitor  
A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems Conference paper
2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
Authors:  Mao F.;  Lu Y.;  Seng-Pan U.;  Martins R.P.
Favorite | View/Download:14/0 | TC[WOS]:0 TC[Scopus]:2 | Submit date:2019/02/11
delay compensation  feedback loop  implantable medical devices  real time  voltage doubler  wireless power transfer  
A 4.06 mW 10-bit 150 MS/s SAR ADC With 1.5-bit/cycle Operation for Medical Imaging Applications Journal article
IEEE SENSORS JOURNAL, 2018,Volume: 18,Issue: 11,Page: 4553-4560
Authors:  Sunny, Sharma;  Chen, Yong;  Boon, Chirn Chye
Favorite | View/Download:23/0 | TC[WOS]:3 TC[Scopus]:4 | Submit date:2018/10/30
1.5-bit/cycle  ADC  capacitive digital-to-analog converter (CDAC)  CMOS  error correction  low power  medical imaging  redundancy  SAR  successive approximation register