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Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 2,Page: 489-501
Authors:  Xing D.;  Zhu Y.;  Chan C.-H.;  Maloberti F.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
reference interference  SAR ADC  time-interleaved scheme  two-step SAR conversion  
Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC Conference paper
Authors:  Wang, Guancheng;  Li, Cheng;  Zhu, Yan;  Zhong, Jianyu;  Lu, Yan;  Chan, Chi-Hang;  Martins, Rui P.
Favorite  |  View/Download:25/0  |  Submit date:2018/10/30
Gain error calibration  testing signal generation  SAR ADC  bridge DAC  low-dropout (LDO) regulator  
A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS Conference paper
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Zheng, Zi-Hao;  Li, Cheng;  Zhong, Jian-Yu;  Martins, Rui P.
Favorite  |  View/Download:19/0  |  Submit date:2018/10/30
Time-interleaved ADC  sampling front-end design  passive sharing  pipelined-SAR ADC  switch bootstrap technique  
Missing-Code-occurrence probability calibration technique for DAC nonlinearity with supply and reference circuit analysis in a SAR ADC Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3707-3719
Authors:  Wang G.;  Li C.;  Zhu Y.;  Zhong J.;  Lu Y.;  Chan C.-H.;  Martins R.P.
Favorite  |  View/Download:3/0  |  Submit date:2019/02/11
bridge DAC  Gain error calibration  low-dropout (LDO) regulator  SAR ADC  testing signal generation  
A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3606-3616
Authors:  Zhu Y.;  Chan C.-H.;  Zheng Z.-H.;  Li C.;  Zhong J.-Y.;  Martins R.P.
Favorite  |  View/Download:2/0  |  Submit date:2019/02/11
passive sharing  pipelined-SAR ADC  sampling front-end design  switch bootstrap technique  Time-interleaved ADC  
An 8.8-GS/s 8b time-interleaved SAR ADC with 50-dB SFDR using complementary dual-loop-assisted buffers in 28nm CMOS Conference paper
Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Authors:  Wang X.S.;  Chan C.-H.;  Du J.;  Wong C.-H.;  Li Y.;  Du Y.;  Kuan Y.-C.;  Hu B.;  Chang M.-C.F.
Favorite  |  View/Download:0/0  |  Submit date:2019/02/14
Nano-Watt Class Energy-Efficient Capacitive Sensor Interface with On-Chip Temperature Drift Compensation Journal article
IEEE Sensors Journal, 2018,Volume: 18,Issue: 7,Page: 2870-2882
Authors:  Zhang T.-T.;  Law M.-K.;  Mak P.-I.;  Vai M.-I.;  Martins R.P.
Favorite  |  View/Download:13/0  |  Submit date:2019/02/11
Capacitive Sensor Interface  Energy Efficiency  High Accuracy  Mismatch Errors  Pressure Sensor  Temperature Compensation  Two-step Incremental-adc  Ultra-low Power  
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download:27/0  |  Submit date:2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
Passive Noise Shaping in SAR ADC With Improved Efficiency Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 2,Page: 416-420
Authors:  Song, Yan;  Chan, Chi-Hang;  Zhu, Yan;  Geng, Li;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download:22/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Delta Sampling  Oversampling  Passive Noise Shaping (Pns)  Successive Approximation Register (Sar)  
A 310 nW 14.2-bit iterative-incremental ADC for wearable sensing systems Conference paper
Proceedings - IEEE International Symposium on Circuits and Systems, Baltimore, MD, MAY 28-31, 2017
Authors:  Zhang T.-T.;  Law M.-K.;  Wang B.;  Mak P.-I.;  Vai M.-I.;  Martins R.P.
Favorite  |  View/Download:9/0  |  Submit date:2019/02/11
Chopping  Dynamic Element Matching  Energy Efficiency  Incremental Adc  Sensor Interface  Two-step  Ultra-low-power  Vearable Sensing System