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A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 9,Page: 3014-3026
Authors:  Chen Y.;  Mak P.-I.;  Boon C.C.;  Martins R.P.
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Bandwidth (Bw)  Cmos  Cross-quadrature Clocking  D-type Flip-flop (Dff)  Data-dependent Jitter (Ddj)  Duobinary  Figure-of-merit (Fom)  Latch  Multi-level Signaling  Multiplexer (Mux)  Selector  Timing Margin