UM

Browse/Search Results:  1-3 of 3 Help

Selected(0)Clear Items/Page:    Sort:
A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs Conference paper
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, France, 30 May-2 June 2010
Authors:  Zhu Y.;  Chan C.-H.;  Chio U.-F.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite  |  View/Download:12/0  |  Submit date:2019/02/11
Parasitic calibration by two-step ratio approaching techinque for split capacitor array SAR ADCs Conference paper
2009 International SoC Design Conference, ISOCC 2009, Busan, South Korea, 22-24 Nov. 2009
Authors:  Wong S.-S.;  Zhu Y.;  Chan C.-H.;  Chio U.-F.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite  |  View/Download:13/0  |  Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Offset Calibration  Parasitic Calibration  Split Capacitor Array  Sucessive Approximation Register (Sar)  
Linearity analysis on a series-split capacitor array for high-speed SAR ADCs Conference paper
2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, Knoxville, TN, AUG 10-13, 2008
Authors:  Yan Zhu;  U-Fat Chio;  He-Gong Wei;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:19/0  |  Submit date:2019/02/11