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Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 2,Page: 489-501
Authors:  Xing D.;  Zhu Y.;  Chan C.-H.;  Maloberti F.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
reference interference  SAR ADC  time-interleaved scheme  two-step SAR conversion  
Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 2,Page: 481-485
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:16/0  |  Submit date:2019/02/13
Bandwidth mismatches  split-digital to analog converter (DAC)  successive-approximation-register (SAR) analog-to-digital converter (ADC)  time-interleaved (TI)  variance based  window detector (WD)  
Serially coupled reversed phase-hydrophilic interaction liquid chromatography-tailored multiple reaction monitoring, a fit-for-purpose tool for large-scale targeted metabolomics of medicinal bile Journal article
ANALYTICA CHIMICA ACTA, 2018,Volume: 1037,Page: 119-129
Authors:  Song, Qingqing;  Liu, Wenjing;  Chen, Xiaojia;  Li, Jun;  Li, Peng;  Yang, Fengqing;  Wang, Yitao;  Song, Yuelin;  Tu, Pengfei
Adobe PDF(1652Kb)  |  Favorite  |  View/Download:403/3  |  Submit date:2018/10/30
Large-scale Targeted Metabolomics  Serially Coupled Rplc-hilic  Tailored Multiple Reaction Monitoring  Medicinal Bile  Bile Acids  
Chemoselective detection of alkyl halides via an iridium(III) luminescent probe Journal article
DYES AND PIGMENTS, 2018,Volume: 159,Page: 479-482
Authors:  Wu, Chun;  Liu, Jin-Biao;  Li, Guodong;  Wong, Suk-Yu;  Han, Quan-Bin;  Leung, Chung-Hang;  Ma, Dik-Lung
View  |  Adobe PDF(687Kb)  |  Favorite  |  View/Download:236/20  |  Submit date:2018/10/30
Alkyl Halides  Iridium  Chemosensor  
Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC Conference paper
Authors:  Wang, Guancheng;  Li, Cheng;  Zhu, Yan;  Zhong, Jianyu;  Lu, Yan;  Chan, Chi-Hang;  Martins, Rui P.
Favorite  |  View/Download:32/0  |  Submit date:2018/10/30
Gain error calibration  testing signal generation  SAR ADC  bridge DAC  low-dropout (LDO) regulator  
A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS Conference paper
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Zheng, Zi-Hao;  Li, Cheng;  Zhong, Jian-Yu;  Martins, Rui P.
Favorite  |  View/Download:26/0  |  Submit date:2018/10/30
Time-interleaved ADC  sampling front-end design  passive sharing  pipelined-SAR ADC  switch bootstrap technique  
Missing-Code-occurrence probability calibration technique for DAC nonlinearity with supply and reference circuit analysis in a SAR ADC Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3707-3719
Authors:  Wang G.;  Li C.;  Zhu Y.;  Zhong J.;  Lu Y.;  Chan C.-H.;  Martins R.P.
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
bridge DAC  Gain error calibration  low-dropout (LDO) regulator  SAR ADC  testing signal generation  
A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3606-3616
Authors:  Zhu Y.;  Chan C.-H.;  Zheng Z.-H.;  Li C.;  Zhong J.-Y.;  Martins R.P.
Favorite  |  View/Download:2/0  |  Submit date:2019/02/11
passive sharing  pipelined-SAR ADC  sampling front-end design  switch bootstrap technique  Time-interleaved ADC  
A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current Conference paper
Authors:  Mao, Jiaji;  Guo, Mingqiang;  Sin, Sai-Weng;  Martins, Rui Paulo
Favorite  |  View/Download:16/0  |  Submit date:2018/10/30
Analog-to-digital conversion  digital background calibration  pipelined ADC  split ADC  opamp-sharing technique  
A 5.35-mW 10-MHz Single-Opamp Third-Order CT Delta Sigma Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS Conference paper
Authors:  Wang, Wei;  Zhu, Yan;  Chan, Chi-Hang;  Martins, Rui Paulo
Favorite  |  View/Download:18/0  |  Submit date:2018/10/30
Terms-Analog-to-digital conversion (ADC)  continuous-time (CT) delta-sigma modulator  DAC driver  passive integrator  single amplifier biquad (SAB)