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Total-Effect Test is Superfluous for Establishing Complementary Mediation Journal article
Statistica Sinica, 2020
Authors:  Yingkai Jiang;  Xinshu Zhao;  Lixing Zhu;  Jun S. Liu;  Ke Deng
View | Adobe PDF | Favorite | View/Download:388/59 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2020/05/11
Complementary Mediation  Hypothesis Testing  Linear Model  Mediation Analysis  Total-effect Test  
A 4.06 mW 10-bit 150 MS/s SAR ADC With 1.5-bit/cycle Operation for Medical Imaging Applications Journal article
IEEE SENSORS JOURNAL, 2018,Volume: 18,Issue: 11,Page: 4553-4560
Authors:  Sunny, Sharma;  Chen, Yong;  Boon, Chirn Chye
Favorite | View/Download:20/0 | TC[WOS]:1 TC[Scopus]:4 | Submit date:2018/10/30
1.5-bit/cycle  ADC  capacitive digital-to-analog converter (CDAC)  CMOS  error correction  low power  medical imaging  redundancy  SAR  successive approximation register  
A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle Operation for Medical Imaging Applications Journal article
IEEE Sensors Journal, 2018,Volume: 18,Issue: 11,Page: 4553-4560
Authors:  Sunny S.;  Chen Y.;  Boon C.C.
Favorite | View/Download:6/0 | TC[WOS]:1 TC[Scopus]:4 | Submit date:2019/02/14
1.5-bit/cycle  ADC  capacitive digital-to-analog converter (CDAC)  CMOS  error correction  low power  medical imaging  redundancy  SAR  successive approximation register  
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite | View/Download:55/0 | TC[WOS]:11 TC[Scopus]:15 | Submit date:2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration Conference paper
2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 5-9 Feb. 2017
Authors:  Chi-Hang Chan;  Yan Zhu;  Iok-Meng Ho;  Wai-Hong Zhang;  Seng-Pan U;  Rui Paulo Martins
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An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 5,Page: 1223-1234
Authors:  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U;  Rui Paulo Martins
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Offset Calibration  Pipelined-successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Sar Logic  
Analog to Digital Converter Circuit Patent
专利类型: 发明专利, 专利号: TWI446723B, 申请日期: 2011-03-08,
Authors:  Sin,S-W(冼世荣);  Ding L(丁立);  Zhu Y(诸嫣);  Wei HG(魏和功);  Chan CH(陈知行);  Chio UF(赵汝法);  U SP(余成斌);  Martins,R(马许愿);  Franco,M
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A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2013,Volume: 48,Issue: 8,Page: 1783-1794
Authors:  Si-Seng Wong;  U-Fat Chio;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
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Analog-to-digital Converter (Adc)  Binary-search Adc  Sar Adc  Time-interleaved  Two-step Adc  
Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption Patent
专利类型: 发明专利, 专利号: US8427355B2, 申请日期: 2011-09-14,
Authors:  Sai-Weng Sin;  Li Ding;  Yan Zhu;  He-Gong Wei;  Chi-Hang Chan;  U-Fat Chio;  Seng-Pan U;  Rui Paulo da Silva Martins;  Franco Maloberti
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N-Bits Successive Approximation Register Analog-to-Digital Converting System Patent
专利类型: 发明专利, 专利号: US8344931B2, 申请日期: 2011-06-01, 公开日期: 2013
Authors:  Yan Zhu;  Chi Hang Chan;  U Fat Chio;  Sai Weng Sin;  Seng Pan U;  Rui Paulo Da Silva Martins;  Franco Maloberti
Favorite | View/Download:28/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/03/30