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Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 2,Page: 489-501
Authors:  Xing D.;  Zhu Y.;  Chan C.-H.;  Maloberti F.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download：5/0  |  Submit date：2019/02/11
reference interference  SAR ADC  time-interleaved scheme  two-step SAR conversion  
Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 2,Page: 481-485
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download：13/0  |  Submit date：2019/02/13
Bandwidth mismatches  split-digital to analog converter (DAC)  successive-approximation-register (SAR) analog-to-digital converter (ADC)  time-interleaved (TI)  variance based  window detector (WD)  
Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019,Volume: 66,Issue: 1,Page: 82-93
Authors:  Li, Cheng;  Chan, Chi-Hang;  Zhu, Yan;  Martins, Rui P.
Favorite  |  View/Download：9/0  |  Submit date：2019/01/17
Reference error  reference buffer  successive-approximation-register (SAR)  analog-to-digital converter (ADC)  reference ripple  
Analysis of Reference Error in High-Speed SAR ADCs with Capacitive DAC Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 1,Page: 82-93
Authors:  Li C.;  Chan C.-H.;  Zhu Y.;  Martins R.P.
Favorite  |  View/Download：13/0  |  Submit date：2019/02/11
analog-to-digital converter (ADC)  reference buffer  Reference error  reference ripple  successive-approximation-register (SAR)  
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler Conference paper
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Authors:  Jiang W.;  Zhu Y.;  Chan C.-H.;  Murmann B.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download：2/0  |  Submit date：2019/02/11
background calibration  current integrating sampler  Time-interleaved ADC  timing skew  
Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC Conference paper
Authors:  Wang, Guancheng;  Li, Cheng;  Zhu, Yan;  Zhong, Jianyu;  Lu, Yan;  Chan, Chi-Hang;  Martins, Rui P.
Favorite  |  View/Download：25/0  |  Submit date：2018/10/30
Gain error calibration  testing signal generation  SAR ADC  bridge DAC  low-dropout (LDO) regulator  
A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS Conference paper
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Zheng, Zi-Hao;  Li, Cheng;  Zhong, Jian-Yu;  Martins, Rui P.
Favorite  |  View/Download：19/0  |  Submit date：2018/10/30
Time-interleaved ADC  sampling front-end design  passive sharing  pipelined-SAR ADC  switch bootstrap technique  
A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018,Volume: 65,Issue: 11,Page: 1534-1538
Authors:  Wang, X. Shawn;  Jin, Xin;  Du, Jieqiong;  Li, Yilei;  Du, Yuan;  Wong, Chien-Heng;  Kuan, Yen-Cheng;  Chan, Chi-Hang;  Chang, Mau-Chung Frank
Favorite  |  View/Download：2/0  |  Submit date：2019/01/17
Analog-to-digital converter (ADC)  virtual-ground sampling  SAR  time-interleaved  
Missing-Code-occurrence probability calibration technique for DAC nonlinearity with supply and reference circuit analysis in a SAR ADC Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3707-3719
Authors:  Wang G.;  Li C.;  Zhu Y.;  Zhong J.;  Lu Y.;  Chan C.-H.;  Martins R.P.
Favorite  |  View/Download：3/0  |  Submit date：2019/02/11
bridge DAC  Gain error calibration  low-dropout (LDO) regulator  SAR ADC  testing signal generation  
A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3606-3616
Authors:  Zhu Y.;  Chan C.-H.;  Zheng Z.-H.;  Li C.;  Zhong J.-Y.;  Martins R.P.
Favorite  |  View/Download：2/0  |  Submit date：2019/02/11
passive sharing  pipelined-SAR ADC  sampling front-end design  switch bootstrap technique  Time-interleaved ADC