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A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS
Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018,Volume: 65,Issue: 11,Page: 1534-1538
Authors:
Wang, X. Shawn
;
Jin, Xin
;
Du, Jieqiong
;
Li, Yilei
;
Du, Yuan
;
Wong, Chien-Heng
;
Kuan, Yen-Cheng
;
Chan, Chi-Hang
;
Chang, Mau-Chung Frank
Favorite
|
View/Download:11/0
|
TC[WOS]:
3
TC[Scopus]:
3
|
Submit date:2019/01/17
Analog-to-digital converter (ADC)
virtual-ground sampling
SAR
time-interleaved
A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS
Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3606-3616
Authors:
Zhu Y.
;
Chan C.-H.
;
Zheng Z.-H.
;
Li C.
;
Zhong J.-Y.
;
Martins R.P.
Favorite
|
View/Download:12/0
|
TC[WOS]:
4
TC[Scopus]:
4
|
Submit date:2019/02/11
passive sharing
pipelined-SAR ADC
sampling front-end design
switch bootstrap technique
Time-interleaved ADC
A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS
Conference paper
Authors:
Zhu, Yan
;
Chan, Chi-Hang
;
Zheng, Zi-Hao
;
Li, Cheng
;
Zhong, Jian-Yu
;
Martins, Rui P.
Favorite
|
View/Download:49/0
|
TC[WOS]:
4
TC[Scopus]:
4
|
Submit date:2018/10/30
Time-interleaved ADC
sampling front-end design
passive sharing
pipelined-SAR ADC
switch bootstrap technique
A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure
Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Honolulu, HI, USA, 18-22 June 2018
Authors:
Song Y.
;
Zhu Y.
;
Chan C.-H.
;
Geng L.
;
Martins R.P.
Favorite
|
View/Download:27/0
|
TC[WOS]:
0
TC[Scopus]:
9
|
Submit date:2019/02/11
A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC
Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017,Volume: 64,Issue: 7,Page: 1684-1695
Authors:
Jianyu Zhong
;
Yan Zhu
;
Chi-Hang Chan
;
Sai-Weng Sin
;
Seng-Pan U
;
Rui Paulo Martins
Favorite
|
View/Download:29/0
|
TC[WOS]:
12
TC[Scopus]:
12
|
Submit date:2019/02/11
Analog-to-digital Converter (Adc)
Low Power
Successive Approximation Architecture
Switched-capacitor Circuits
A 12b 180MS/s 0.068mm(2) With Full-Calibration-Integrated Pipelined-SAR ADC
Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 7,Page: 1684-1695
Authors:
Zhong, Jianyu
;
Zhu, Yan
;
Chan, Chi-Hang
;
Sin, Sai-Weng
;
U, Seng-Pan
;
Martins, Rui Paulo
Favorite
|
View/Download:30/0
|
TC[WOS]:
12
TC[Scopus]:
12
|
Submit date:2018/10/30
Analog-to-digital converter (ADC)
successive approximation architecture
low power
switched-capacitor circuits
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations
Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017,Volume: 25,Issue: 1,Page: 354-363
Authors:
Zhu, Yan
;
Chan, Chi-Hang
;
Pan, Seng U.
;
Martins, Rui Paulo
Favorite
|
View/Download:31/0
|
TC[WOS]:
8
TC[Scopus]:
8
|
Submit date:2018/10/30
Offset Calibration
Partial Interleaving (Pi)
Pipelined-sar
Stage-gain Error Calibration
A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction
Conference paper
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, 12-15 Sept. 2016
Authors:
Jianyu Zhong
;
Yan Zhu
;
Chi-Hang Chan
;
Sai-Weng Sin
;
Seng-Pan U
;
R. P. Martins
Favorite
|
View/Download:26/0
|
TC[WOS]:
9
TC[Scopus]:
9
|
Submit date:2019/02/11
An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS
Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 5,Page: 1223-1234
Authors:
Yan Zhu
;
Chi-Hang Chan
;
Seng-Pan U
;
Rui Paulo Martins
Favorite
|
View/Download:21/0
|
TC[WOS]:
19
TC[Scopus]:
21
|
Submit date:2019/02/11
Offset Calibration
Pipelined-successive Approximation Register (Sar) Analog-to-digital Converter (Adc)
Sar Logic
Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs
Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2015,Volume: 62,Issue: 9,Page: 2196-2206
Authors:
Jianyu Zhong
;
Yan Zhu
;
Sai-Weng Sin
;
Seng-Pan U
;
Rui Paulo Martins
Favorite
|
View/Download:16/0
|
TC[WOS]:
16
TC[Scopus]:
16
|
Submit date:2019/02/11
Analog-to-digital Converter (Adc)
Reference Noise
Successive-approximation-register (Sar) Adc
Thermal Noise