UM

Browse/Search Results:  1-10 of 22 Help

Selected(0)Clear Items/Page:    Sort:
16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur Conference paper
2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, USA, 17-21 Feb. 2019
Authors:  Zunsong Yang;  Yong Chen;  Shiheng Yang;  Pui-In Mak;  Rui P. Martins
Favorite  |  View/Download:79/0  |  Submit date:2019/03/13
A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2019,Page: 1 - 12
Authors:  Shiheng Yang;  Jun Yin;  Haidong Yi;  Wei-Han Yu;  Pui-In Mak;  Rui P. Martins
Favorite  |  View/Download:35/0  |  Submit date:2019/03/12
Bluetooth Low Energy (Ble)  Cmos  Energy Harvesting  Master-slave Sampling Filter (Mssf)  Micropower Manager (Μpm)  Phase-locked Loop (Pll)  Power Amplifier (Pa)  Power Gating  Transmitter (Tx)  Ultralow-voltage (Ulv)  Voltage-controlled Oscillator (Vco)  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 1,Page: 88-98
Authors:  Yang S.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:25/0  |  Submit date:2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A 0.0056mm2all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrmsJitter and -249dB FOM Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, United states, 2 11, 2018 - 2 15, 2018
Authors:  Yang, Shiheng;  Yin, Jun;  Mak, Pui-In;  Martins, Rui P.
Favorite  |  View/Download:11/0  |  Submit date:2018/11/06
A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, FEB 11-15, 2018
Authors:  Shiheng Yang;  Jun Yin;  Pui-In Mak;  Rui P. Martins
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS Conference paper
2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, USA, FEB 11-15, 2018
Authors:  Jun Yin;  Shiheng Yang;  Haidong Yi;  Wei-Han Yu;  Pui-In Mak;  Rui P. Martins
Favorite  |  View/Download:17/0  |  Submit date:2018/11/06
A 0.003mm2 1.7-to-3.5GHz dual-mode time-interleaved ring-VCO achieving 90-to-150kHz 1/f3 phase-noise corner Conference paper
2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, United states, 1 31, 2016 - 2 4, 2016
Authors:  Jun Yin;  Pui-In Mak;  Franco Maloberti;  Rui P. Martins
Favorite  |  View/Download:14/0  |  Submit date:2018/11/06
A Time-Interleaved Ring-VCO with Reduced 1/f3 Phase Noise Corner, Extended Tuning Range and Inherent Divided Output Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 12,Page: 2979-2991
Authors:  Yin J.;  Mak P.-I.;  Maloberti F.;  Martins R.P.
Favorite  |  View/Download:13/0  |  Submit date:2019/02/11
1/f3 Phase Noise Corner  Divided Output  Flicker Noise  Impulse Sensitivity Function (Isf)  Phase Combiner  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Supply Voltage  Time-interleaved (Ti).  
An all-factor modulation bandwidth extension technique for delta-sigma PLL transmitter Conference paper
TENCON 2015 - 2015 IEEE Region 10 Conference, Macao, China, 1-4 Nov. 2015
Authors:  Mo Huang;  Yan Lu;  Xiao-ming Xiong;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:14/0  |  Submit date:2019/02/11
Delta-sigma  Transmitters  Modulation Bandwidth Extension  Phase Locked Loop (Pll)  
Transformer-Based Design Techniques for Oscillators and Frequency Dividers Book
Switzerland:Springer, 2016
Authors:  Howard Cam Luong;  Jun Yin
Favorite  |  View/Download:5/0  |  Submit date:2019/04/03
Cmos Pll Synthesizers  Voltage-controlled Oscillators  Mm-wave Integrated Circuits And Systems  Cmos Radio-frequency Integrated Circuits  Integrated Frequency Synthesizers For Wireless Systems  Low Power Vco Design  Low-voltage Cmos Rf Frequency  Oscillators And Frequency Dividers  Phase-locked Loops  Synthesizers