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Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC
Conference paper
Authors:
Wang, Guancheng
;
Li, Cheng
;
Zhu, Yan
;
Zhong, Jianyu
;
Lu, Yan
;
Chan, Chi-Hang
;
Martins, Rui P.
Favorite
|
View/Download:49/0
|
TC[WOS]:
0
TC[Scopus]:
2
|
Submit date:2018/10/30
Gain error calibration
testing signal generation
SAR ADC
bridge DAC
low-dropout (LDO) regulator
Missing-Code-occurrence probability calibration technique for DAC nonlinearity with supply and reference circuit analysis in a SAR ADC
Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3707-3719
Authors:
Wang G.
;
Li C.
;
Zhu Y.
;
Zhong J.
;
Lu Y.
;
Chan C.-H.
;
Martins R.P.
Favorite
|
View/Download:16/0
|
TC[WOS]:
0
TC[Scopus]:
2
|
Submit date:2019/02/11
bridge DAC
Gain error calibration
low-dropout (LDO) regulator
SAR ADC
testing signal generation
Authentic compound-free strategy for simultaneous determination of primary coumarins in Peucedani Radix using offline high performance liquid chromatography-nuclear magnetic resonance spectroscopy-tandem mass spectrometry
Journal article
ACTA PHARMACEUTICA SINICA B, 2018,Volume: 8,Issue: 4,Page: 645-654
Authors:
Liu, Yao
;
Song, Qingqing
;
Liu, Wenjing
;
Li, Peng
;
Li, Jun
;
Zhao, Yunfang
;
Zhang, Liang
;
Tu, Pengfei
;
Wang, Yitao
;
Song, Yuelin
View
|
Adobe PDF
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Favorite
|
View/Download:548/27
|
TC[WOS]:
5
TC[Scopus]:
10
|
Submit date:2018/10/30
Authentic Compound-independent Quantitation
Offline Lcnmrms/ms
Automated Fraction Collection Module
Quantitative H-1 Nmr
Peucedani Radix
Regio-specific Monitoring
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration
Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:
Chan, Chi-Hang
;
Zhu, Yan
;
Zhang, Wai-Hong
;
Seng-Pan, U.
;
Martins, Rui Paulo
Favorite
|
View/Download:55/0
|
TC[WOS]:
11
TC[Scopus]:
15
|
Submit date:2018/10/30
1-then-2 B/cycle Sar Adc
Analog-to-digital Conversion
Background Offset Calibration
Multi-bit/cycle Sar Adc
Time Interleaving
A 12b 180MS/s 0.068mm(2) With Full-Calibration-Integrated Pipelined-SAR ADC
Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 7,Page: 1684-1695
Authors:
Zhong, Jianyu
;
Zhu, Yan
;
Chan, Chi-Hang
;
Sin, Sai-Weng
;
U, Seng-Pan
;
Martins, Rui Paulo
Favorite
|
View/Download:29/0
|
TC[WOS]:
9
TC[Scopus]:
12
|
Submit date:2018/10/30
Analog-to-digital converter (ADC)
successive approximation architecture
low power
switched-capacitor circuits
A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC
Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017,Volume: 64,Issue: 7,Page: 1684-1695
Authors:
Jianyu Zhong
;
Yan Zhu
;
Chi-Hang Chan
;
Sai-Weng Sin
;
Seng-Pan U
;
Rui Paulo Martins
Favorite
|
View/Download:27/0
|
TC[WOS]:
9
TC[Scopus]:
12
|
Submit date:2019/02/11
Analog-to-digital Converter (Adc)
Low Power
Successive Approximation Architecture
Switched-capacitor Circuits
A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration
Conference paper
2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 5-9 Feb. 2017
Authors:
Chi-Hang Chan
;
Yan Zhu
;
Iok-Meng Ho
;
Wai-Hong Zhang
;
Seng-Pan U
;
Rui Paulo Martins
Favorite
|
View/Download:23/0
|
TC[WOS]:
18
TC[Scopus]:
24
|
Submit date:2018/11/06
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations
Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017,Volume: 25,Issue: 1,Page: 354-363
Authors:
Zhu, Yan
;
Chan, Chi-Hang
;
Pan, Seng U.
;
Martins, Rui Paulo
Favorite
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View/Download:30/0
|
TC[WOS]:
7
TC[Scopus]:
8
|
Submit date:2018/10/30
Offset Calibration
Partial Interleaving (Pi)
Pipelined-sar
Stage-gain Error Calibration
A 4x time-domain interpolation 6-bit 3.4 Gs/s 12.6 mw flash ADC in 65 nm CMOS
Journal article
Journal of Semiconductor Technology and Science, 2016,Volume: 16,Issue: 4,Page: 395-404
Authors:
Jianwei Liu
;
Chi-Hang Chan
;
Sai-Weng Sin
;
Seng-Pan U
;
Rui Paulo Martins
Favorite
|
View/Download:20/0
|
TC[WOS]:
0
TC[Scopus]:
1
|
Submit date:2019/02/11
4x Time-domain Interpolation
Flash Adc
Sr-latch
Time Comparator
An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS
Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 5,Page: 1223-1234
Authors:
Yan Zhu
;
Chi-Hang Chan
;
Seng-Pan U
;
Rui Paulo Martins
Favorite
|
View/Download:20/0
|
TC[WOS]:
16
TC[Scopus]:
20
|
Submit date:2019/02/11
Offset Calibration
Pipelined-successive Approximation Register (Sar) Analog-to-digital Converter (Adc)
Sar Logic