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| Total-Effect Test is Superfluous for Establishing Complementary Mediation Journal article
Statistica Sinica, 2020
Authors: Yingkai Jiang; Xinshu Zhao ; Lixing Zhu; Jun S. Liu; Ke Deng
 View |  Adobe PDF |  Favorite | View/Download：388/59 | TC[WOS]:0 TC[Scopus]:0 | Submit date：2020/05/11
Complementary Mediation Hypothesis Testing Linear Model Mediation Analysis Total-effect Test |
| A 13-bit 8-kS/s δ ∑ Readout IC Using ZCB Integrators with an Embedded Resistive Sensor Achieving 1.05-pJ/Conversion Step and a 65-dB PSRR Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 4,Page: 843-853
Authors: Li，Bing; Na，Ji Ping; Wang，Wei; Liu，Jia; Yang，Qian; Mak，Pui In
 Favorite | View/Download：22/0 | TC[WOS]:1 TC[Scopus]:2 | Submit date：2019/08/22
CMOS figure of merit (FoM) oversampling Δ-Σ modulation power-supply rejection ratio (PSRR) readout IC (ROIC) resistive sensor Wheatstone bridge zero-crossing-based (ZCB) integrator |
| A 13-bit 8-kS/s δ ∑ Readout IC Using ZCB Integrators with an Embedded Resistive Sensor Achieving 1.05-pJ/Conversion Step and a 65-dB PSRR Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 4,Page: 843-853
Authors: Li，Bing; Na，Ji Ping; Wang，Wei; Liu，Jia; Yang，Qian; Mak，Pui In
Favorite | View/Download：71/0 | TC[WOS]:2 TC[Scopus]:2 | Submit date：2020/12/04
CMOS figure of merit (FoM) oversampling Δ-Σ modulation power-supply rejection ratio (PSRR) readout IC (ROIC) resistive sensor Wheatstone bridge zero-crossing-based (ZCB) integrator |
| Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 2,Page: 489-501
Authors: Xing D.; Zhu Y.; Chan C.-H.; Maloberti F.; Seng-Pan U.; Martins R.P.
Favorite | View/Download：23/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date：2019/02/11
reference interference SAR ADC time-interleaved scheme two-step SAR conversion |
| A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 2,Page: 157-161
Authors: Jiang T.; Yin J.; Mak P.-I.; Martins R.P.
Favorite | View/Download：28/0 | TC[WOS]:1 TC[Scopus]:2 | Submit date：2019/02/14
Bootstrap (Bt) Low Voltage Non-overlapping Clock Phase Noise Ring Voltage-controlled Oscillator (Rvco) |
| A 0.044-mm2 0.5-To-7-GHz Resistor-Plus-Source-Follower-Feedback Noise-Cancelling LNA Achieving a Flat NF of 3.3±0.45 dB Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 1,Page: 71-75
Authors: Yu H.; Chen Y.; Boon C.C.; Li C.; Mak P.-I.; Martins R.P.
Favorite | View/Download：37/0 | TC[WOS]:9 TC[Scopus]:16 | Submit date：2019/02/11
Cmos Low-noise Amplifier (Lna) Noise Cancelling Noise Figure (Nf) Resistor Feedback Source Follower Feedback (Sff) Wideband Input Impedance Matching |
| A coin-battery-powered LDO-Free 2.4-GHz Bluetooth Low Energy/ZigBee receiver consuming 2 mA Journal article
Integration, 2019
Authors: Balan Z.; Ramiah H.; Rajendran J.; Vitee N.; Shasidharan P.N.; Yin J.; Mak P.-I.; Martins R.P.
Favorite | View/Download：9/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date：2019/02/11
Bluetooth Low Energy (BLE) CMOS receiver Current-reuse Forward body bias I/Q mixers Low power Quadrature LNA Voltage-controlled oscillator (VCO) ZigBee |
| A 5.1-to-7.3 mW, 2.4-to-5 GHz Class-C Mode-Switching Single-Ended-Complementary VCO Achieving >190 dBc/Hz FoM Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 2,Page: 237-241
Authors: Lim C.C.; Ramiah H.; Yin J.; Kumar N.; Mak P.-I.; Martins R.P.
Favorite | View/Download：23/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date：2019/02/14
Class-c Cmos Current-reuse Mode Switching Phase Noise (Pn) Single-ended Complementary (Sec) Voltage-controlled Oscillator (Vco) Wideband |
| An Inverse-Class-F CMOS Oscillator With Intrinsic-High-Q First Harmonic and Second Harmonic Resonances Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 12,Page: 3528-3539
Authors: Lim, Chee Cheow; Ramiah, Harikrishnan; Yin, Jun; Mak, Pui-In; Martins, Rui P.
Favorite | View/Download：10/0 | TC[WOS]:1 TC[Scopus]:8 | Submit date：2019/01/17
Figure of merit (FoM) flicker noise upcon-version inverse-class-F (class-F-1) oscillator phase noise (PN) second harmonic resonance voltage-biased oscillator |
| An Inverse-Class-F CMOS Oscillator with Intrinsic-High-Q 1st-Harmonic and 2nd-Harmonic Resonances Journal article
IEEE Journal of Solid-State Circuits, 2018,Volume: 53,Issue: 12,Page: 3528 - 3539
Authors: Chee Cheow Lim; Harikrishnan Ramiah; Jun Yin; Pui-In Mak; Rui P. Martins
Favorite | View/Download：31/0 | TC[WOS]:1 TC[Scopus]:8 | Submit date：2019/03/12
Figure Of Merit (Fom) Flicker Noise Upconversion Inverse-class-f (Class-f−1) Oscillator Phase Noise (Pn) Second Harmonic Resonance Voltage-biased Oscillator |
