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20.7 A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling and Quantization Scheme in Backend Subranging QTZ Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Authors:  Wang，Wei;  Chan，Chi Hang;  Zhu，Yan;  Martins，Rui P.
Favorite | View/Download：73/0 | TC[WOS]:0 TC[Scopus]:5 | Submit date：2020/12/04
16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur Conference paper
2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, USA, 17-21 Feb. 2019
Authors:  Zunsong Yang;  Yong Chen;  Shiheng Yang;  Pui-In Mak;  Rui P. Martins
Favorite | View/Download：90/0 | TC[WOS]:0 TC[Scopus]:17 | Submit date：2019/03/13
A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2019,Page: 1 - 12
Authors:  Shiheng Yang;  Jun Yin;  Haidong Yi;  Wei-Han Yu;  Pui-In Mak;  Rui P. Martins
Favorite | View/Download：47/0 | TC[WOS]:0 TC[Scopus]:8 | Submit date：2019/03/12
Bluetooth Low Energy (Ble)  Cmos  Energy Harvesting  Master-slave Sampling Filter (Mssf)  Micropower Manager (Μpm)  Phase-locked Loop (Pll)  Power Amplifier (Pa)  Power Gating  Transmitter (Tx)  Ultralow-voltage (Ulv)  Voltage-controlled Oscillator (Vco)  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 1,Page: 88-98
Authors:  Yang S.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite | View/Download：32/0 | TC[WOS]:9 TC[Scopus]:10 | Submit date：2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 9,Page: 3014-3026
Authors:  Chen Y.;  Mak P.-I.;  Boon C.C.;  Martins R.P.
Favorite | View/Download：16/0 | TC[WOS]:5 TC[Scopus]:5 | Submit date：2019/02/11
Bandwidth (Bw)  Cmos  Cross-quadrature Clocking  D-type Flip-flop (Dff)  Data-dependent Jitter (Ddj)  Duobinary  Figure-of-merit (Fom)  Latch  Multi-level Signaling  Multiplexer (Mux)  Selector  Timing Margin  
Analysis of common-mode interference and jitter of clock receiver circuits with improved topology Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 6,Page: 1819-1829
Authors:  Yang X.;  Zhu Y.;  Chan C.-H.;  Seng-Pan U.;  Martins R.P.
Favorite | View/Download：17/0 | TC[WOS]:4 TC[Scopus]:5 | Submit date：2019/02/11
Isf  Low Clock Jitter Circuit  Self-bias  
A 0.0056mm2all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrmsJitter and -249dB FOM Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, United states, 2 11, 2018 - 2 15, 2018
Authors:  Yang, Shiheng;  Yin, Jun;  Mak, Pui-In;  Martins, Rui P.
Favorite | View/Download：20/0 | TC[WOS]:0 TC[Scopus]:12 | Submit date：2018/11/06
A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, FEB 11-15, 2018
Authors:  Shiheng Yang;  Jun Yin;  Pui-In Mak;  Rui P. Martins
Favorite | View/Download：10/0 | TC[WOS]:14 TC[Scopus]:12 | Submit date：2019/02/11
A 0.013-mm(2) 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 3,Page: 599-603
Authors:  Balachandran, Arya;  Chen, Yong;  Boon, Chirn Chye
Favorite | View/Download：21/0 | TC[WOS]:1 TC[Scopus]:2 | Submit date：2018/10/30
Channel loss  CMOS equalizer  continuous-time linear equalizer (CTLE)  figure of merit (FOM)  inductorless  intersymbol interference (ISI)  low-frequency equalization (LFEQ)  
0.058 mm(2) 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss Journal article
ELECTRONICS LETTERS, 2018,Volume: 54,Issue: 2
Authors:  Balachandran, Arya;  Chen, Yong;  Choi, Pilsoon;  Boon, Chirn Chye
Favorite | View/Download：24/0 | TC[WOS]:1 TC[Scopus]:3 | Submit date：2018/10/30
equalisers  circuit feedback  analogue circuits  random sequences  binary sequences  CMOS analogue integrated circuits  inductorless analogue equaliser  low-frequency equalisation compensation  LFEQ  low-frequency channel loss  active feedback topology  negative capacitance circuit  data jitter  pseudorandom binary sequence  CMOS technology  loss 15 dB  bit rate 13 Gbit  s  size 65 nm  voltage 1  2 V