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A 0.0056mm2all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrmsJitter and -249dB FOM Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, United states, 2 11, 2018 - 2 15, 2018
作者:  Yang, Shiheng;  Yin, Jun;  Mak, Pui-In;  Martins, Rui P.
收藏  |  浏览/下载:5/0  |  提交时间:2018/11/06
A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, FEB 11-15, 2018
作者:  Shiheng Yang;  Jun Yin;  Pui-In Mak;  Rui P. Martins
收藏  |  浏览/下载:6/0  |  提交时间:2019/02/11
Two-step channel selection technique by programmable digital-double quadrature sampling for complex low-IF receivers Journal article
Electronics Letters, 2003,Volume: 39,Issue: 11,Page: 825-827
作者:  Mak P.-I.;  Seng-Pan U;  Martins R.P.
收藏  |  浏览/下载:6/0  |  提交时间:2019/02/11
Channel Allocation  Digital Phase Locked Loops  Phase Noise  Frequency Synthesizers